1. 1Registers and Counters Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.

2. Registers and Counters2 Sequential circuits are classified based in their function, e.g., registers. Register: A group of flip-flops each storing one bit of information. Registers include flip-flops and gates: flip-flops hold the information, gates control how the information is transferred to the register. Counter is a register that goes through a predetermined sequence of states.

3. Registers and Counters3 What good are registers? Flip-flops are limited because they can store only one bit. – We had to use two flip-flops for our two-bit counter examples. – Most computers work with integers and single-precision floating- point numbers that are 32-bits long. Registers are commonly used as temporary storage in a processor. – They are faster and more convenient than main memory. – More registers can help speed up complex calculations. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

4. Registers and Counters4 4-bit Register Loads in parallel Clear: Cleans the output to all 0’s. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

5. Registers and Counters5 Register with Parallel Load To fully synchronize the system clock signals should arrive at the same time at all flip-flops. Therefore we do not control the clock by gates. Load = 1, we load data Load =0, register content does not change 1 I0 I3 I2 I1 1 1 1 1 1 Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

6. Registers and Counters6 Implementing sequential circuits Using a register with parallel load capability, one can implement arbitrary sequential circuits. The register can act as the memory component. Combinational Logic Register Input Output Sequential Circuit

7. Registers and Counters7 Example Present Input Next Output State State A 1 A 2 x A 1 A 2 Y 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0 1 A) State table A1A1 0 0 1 0 0 1 A1A1 A2A2 X A 1 = A 1 X’ 0 1 X A 2 = A’ 2 X+ A 2 X = A 2  X 0 0 1 0 X Y = A 2 X A1A1 A2A2 A2A2

8. Registers and Counters8.. with a combinational circuit A1A1 A 2 y b) Logic Diagram

9. Registers and Counters9 … with ROM Address Outputs 1 2 3 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0 1 ROM truth table A1A1 A 2 y 1 2 3 8 x 3 ROM

10. Registers and Counters10 Shift Registers A register capable of shifting its binary information in one or both directions is called the shift register. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

11. Registers and Counters11 Serial transfer Clocked 4 times Why do this? Maybe these are far apart Could shift data in What’s on wire at each clock? Slides adapted from Anselmo Lastra U. of North Carolina at Chapel Hill

12. Registers and Counters12 Table Showing Shift Slides adapted from Anselmo Lastra U. of North Carolina at Chapel Hill A digital system is in the serial mode when information is processed one bit at a time.

13. Registers and Counters13 Serial data transfer One application of shift registers is converting between “serial data” and “parallel data.” Computers typically work with multiple-bit quantities. – ASCII text characters are 8 bits long. – Integers, single-precision floating-point numbers, and screen pixels are up to 32 bits long. But sometimes it’s necessary to send or receive data serially, or one bit at a time. Some examples include: – Input devices such as keyboards and mice. – Output devices like printers. – Any serial port, USB or Firewire device transfers data serially.

14. Registers and Counters14 Receiving serial data To receive serial data using a shift register: – The serial device is connected to the register’s SI input. – The shift register outputs Q3-Q0 are connected to the computer. The serial device transmits one bit of data per clock cycle. – These bits go into the SI input of the shift register. – After four clock cycles, the shift register will hold a four-bit word. The computer then reads all four bits at once from the Q3-Q0 outputs. serial device computer

15. Registers and Counters15 Sending data serially To send data serially with a shift register, you do the opposite: – The CPU is connected to the register’s D inputs. – The shift output (Q3 in this case) is connected to the serial device. The computer first stores a four-bit word in the register, in one cycle. The serial device can then read the shift output. – One bit appears on Q3 on each clock cycle. – After four cycles, the entire four-bit word will have been sent. serial device computer

16. Registers and Counters16 Remember 4-bit Parallel Adder Circuit? Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

17. Registers and Counters17 Serial Addition Slower compared to parallel addition, but uses less equipment. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

18. Registers and Counters18 Serial Adder vs. Parallel Adder PA uses registers with parallel load, SA uses shift registers. PA uses more FAs compared to SA. Excluding the registers, PA is a combinational circuit, SA is sequential. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

19. Registers and Counters19 Serial Adder: Design Procedure State Table for a Serial Adder: Present State Inputs Next State Output Flip-Flop inputs Q x y Q S J0 K0 0 0 0 0 0 0 x 0 0 1 0 1 0 x 0 1 0 0 1 0 x 0 1 1 1 0 1 x 1 0 0 0 1 x 1 1 0 1 1 0 x 0 1 1 0 1 0 x 0 1 1 1 1 1 x 0 J0=xy K0=x’y’= (x+y)’ S=x XOR y XOR z Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

20. Registers and Counters20 Serial 4-bit Parallel Adder Circuit Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

21. Registers and Counters21 Universal Shift Register A register capable of shifting in both directions and loading in parallel. Multiplexer Inputs: 0: No Change 1:Shift Right 2:Shift Left 3:Parallel load Controls information transfer Stores Information Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

22. Registers and Counters22 Serial vs. parallel: pros and cons Serial vs. parallel adder One full adder vs. n adders Serial takes n units of time, parallel only one Slides adapted from Anselmo Lastra U. of North Carolina at Chapel Hill

23. Registers and Counters23 Counters A register that goes trough a prescribed sequence of states is called a counter. Binary counter – Counts through binary sequence – n bit counter counts from 0 to 2n There are two groups of counters: Ripple counters and Synchronous counters. Ripple counters: The flip-flop output triggers other flip-flops. Synchronous counters count the clock.

24. Registers and Counters24 What good are counters? Counters can act as simple clocks to keep track of “time.” You may need to record how many times something has happened. – How many bits have been sent or received? – How many steps have been performed in some computation? All processors contain a program counter, or PC. – Programs consist of a list of instructions that are to be executed one after another (for the most part). – The PC keeps track of the instruction currently being executed. – The PC increments once on each clock cycle, and the next program instruction is then executed.

25. Registers and Counters25 Binary Ripple Counter A binary ripple counter consists of a series of complementing flip-flops, with the output of each flip-flop connected to the next higher order. Examples of complementing flip-flops are T and D (with the output complement connected to the input) flip-flop. Binary Count Sequence A3 A2 A1 A0 0 0 0 0 A0 is complemented with each count pulse 0 0 0 1 A1 is complemented when A0 goes from 1 to 0 0 0 1 0 A2 is complemented when A1 goes from 1 to 0 0 0 1 1 A3 is complemented when A2 goes from 1 to 0 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

26. Registers and Counters26 Examples of Binary Ripple Counters No clocks! Why is the Count is negated at the clock input? Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca count

27. Registers and Counters27 Binary Ripple Counter Count-down counter: A binary counter with reverse count: Starts from 15 goes down. In a count-down counter the least significant bit is complemented with every count pulse. Any other bit is complemented if the previous bit goes from 0 to 1. We can use the same counter design with negative edge flip-flops to make a count-down flip-flop. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

28. Registers and Counters28 BCD Ripple Counter A BCD counter starts from 0 ends at 9. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

29. Registers and Counters29 Logic Diagram of BCD Ripple Counter Q1 is applied to the C inputs of Q2 and Q8 Q2 is applied to the C input of Q4 J and K are connected to either 1 or flip- flop outputs Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

30. Registers and Counters30 Logic Diagram of BCD Ripple Counter Verification: Does the circuit follow the states? Q1 is complemented with every count (J=K=1) ‏ Q2 complements if Q1 goes from 1 to 0 and Q8 is 0 Q2 remains 0 if Q8 becomes 1 Q4 complements if Q2 goes from 1 to 0 Q8 remains 0 as long as Q2 or Q4 is 0 When Q2 and Q4 are 1, Q8 complements when Q1 goes from 1 to 0. Q8 clears and the next Q1 transition. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

31. Registers and Counters31 Three-Decade Decimal BCD Counter Counts from 0 to 999: When Q8 goes from 1 to 0 the next higher order decade is triggered Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

32. Registers and Counters32 4-bit Synchronous Binary Counters A flip-flop is complemented if all lower bits are 1. A3 A2 A1 A0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

33. Registers and Counters33 4-bit Up-Down Binary Counters In a down binary counter a) The least significant bit is always complemented b) a bit is complemented if all lower bits are 0. Change an up counter to a down counter: The AND gates should come from the complement outputs instead of the normal one Up = 1, Down =0: Circuit counts up since input comes from Normal output Up = 0, Down =1: Circuit counts down since input comes from Complemented output Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

34. Registers and Counters34 Binary Counter with Parallel Load Sometimes we need an initial value prior to the count operation. Initial value: I3 I2 I1 I0 Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

35. Registers and Counters35 Binary Counter with Parallel Load Count = 1, Load =0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca 1

36. Registers and Counters36 Binary Counter with Parallel Load Count = 0, Load =1 0 1 0 0 I0 1 1 1 1 1 1 1 1 1 1 1 1 I3’ I0’ 0 I1 I1’ I2 I2’ I3 I1 Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

37. Registers and Counters37 BCD counter with parallel load In part a, 1001 (9) is detected. In part b, 1010 (10) is detected. Why? In part a, LOAD is set to 1 and effective next cycle. (LOAD is a synchronous control input) In part b, counter is immediately cleared. (Clear is an asynchronous control input) ‏ Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

38. Registers and Counters38 Counters with unused states The examples shown so far have all had 2 n states, and used n flip-flops. But sometimes you may have unused, leftover states. For example, here is a state table and diagram for a counter that repeatedly counts from 0 (000) to 5 (101). What should we put in the table for the two unused states? 001 010 011 100 101 000

39. Registers and Counters39 Unused states can be don’t cares… To get the simplest possible circuit, you can fill in don’t cares for the next states. This will also result in don’t cares for the flip-flop inputs, which can simplify the hardware. If the circuit somehow ends up in one of the unused states (110 or 111), its behavior will depend on exactly what the don’t cares were filled in with. 001 010 011 100 101 000

40. Registers and Counters40 …or maybe you do care To get the safest possible circuit, you can explicitly fill in next states for the unused states 110 and 111. This guarantees that even if the circuit somehow enters an unused state, it will eventually end up in a valid state. This is called a self-starting counter. 001 010 011 100 101 000 111 110

41. Registers and Counters41 Other Counters: Ring Counter A ring counter is a counter with ONLY 1 flip-flop set to 1 at any particular time, all other are cleared. Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

42. Registers and Counters42 Other Counters: Johnson Counter A 4 flip-flop ring counter that produces 8 states (not 4). Slides adapted from Amirali Baniasadi amirali@ece.uvic.ca

43. Registers and Counters43 Registers - summary A register is a special state machine that stores multiple bits of data. Several variations are possible: – Parallel loading to store data into the register. – Shifting the register contents either left or right. – Counters are considered a type of register too! One application of shift registers is converting between serial and parallel data. Registers are a central part of modern processors, as we will see in coming weeks.

44. Registers and Counters44 Counters - Summary Counters serve many purposes in sequential logic design. There are lots of variations on the basic counter. – Some can increment or decrement. – An enable signal can be added. – The counter’s value may be explicitly set. There are also several ways to make counters. – You can follow the sequential design principles from last week to build counters from scratch. – You could also modify or combine existing counter devices.

45. Registers and Counters45 RAM: Random access memory Sequential circuits all depend upon the presence of memory. – A flip-flop can store one bit of information. – A register can store a single “word,” typically 32-64 bits. Random access memory, or RAM, allows us to store even larger amounts of data. – The basic interface to memory. – How you can implement static RAM chips hierarchically. This is the last piece we need to put together a computer!

46. Registers and Counters46 Introduction to RAM Random-access memory, or RAM, provides large quantities of temporary storage in a computer system. Remember the basic capabilities of a memory: – It should be able to store a value. – You should be able to read the value that was saved. – You should be able to change the stored value. A RAM is similar, except that it can store many values. – An address will specify which memory value we’re interested in. – Each value can be a multiple-bit word (e.g., 32 bits). We’ll refine the memory properties as follows: A RAM should be able to: - Store many words, one per address - Read the word that was saved at a particular address - Change the word that’s saved at a particular address

47. Registers and Counters47 Picture of memory You can think of computer memory as being one big array of data. – The address serves as an array index. – Each address refers to one word of data. You can read or modify the data at any given memory address, just like you can read or modify the contents of an array at any given index. If you’ve worked with pointers in C or C++, then you’ve already worked with memory addresses.

48. Registers and Counters48 Block diagram of RAM This block diagram introduces the main interface to RAM. – A Chip Select, CS, enables or disables the RAM. – ADRS specifies the address or location to read from or write to. – WR selects between reading from or writing to the memory.  To read from memory, WR should be set to 0. OUT will be the n-bit value stored at ADRS.  To write to memory, we set WR = 1. DATA is the n-bit value to save in memory. This interface makes it easy to combine RAMs together, as we’ll see. 2 k x n memory ADRSOUT DATA CS WR k n n

49. Registers and Counters49 Memory sizes We refer to this as a 2 k x n memory. – There are k address lines, which can specify one of 2 k addresses. – Each address contains an n-bit word. For example, a 2 24 x 16 RAM contains 2 24 = 16M words, each 16 bits long. – The RAM would need 24 address lines. – The total storage capacity is 2 24 x 16 = 2 28 bits. 2 k x n memory ADRSOUT DATA CS WR k n n

50. Registers and Counters50 Size matters! Memory sizes are usually specified in numbers of bytes (8 bits). The 2 28 -bit memory on the previous page translates into: 2 28 bits / 8 bits per byte = 2 25 bytes With the abbreviations below, this is equivalent to 32 megabytes. To confuse you, RAM size is measured in base 2 units, while hard drive size is measured in base 10 units. – In this class, we’ll only concern ourselves with the base 2 units.

51. Registers and Counters51 Typical memory sizes Some typical memory capacities: – PCs usually come with 256-4096MB RAM. – PDAs have 64-512MB of memory. – Digital cameras and MP3 players can have 512MB or more of storage. Many operating systems implement virtual memory, which makes the memory seem larger than it really is. – Most systems allow up to 32-bit addresses. This works out to 2 32, or about four billion, different possible addresses. – With a data size of one byte, the result is apparently a 4GB memory! – The operating system uses hard disk space as a substitute for “real” memory.

52. Registers and Counters52 Reading RAM To read from this RAM, the controlling circuit must: – Enable the chip by ensuring CS = 1. – Select the read operation, by setting WR = 0. – Send the desired address to the ADRS input. – The contents of that address appear on OUT after a little while. Notice that the DATA input is unused for read operations. 2 k x n memory ADRSOUT DATA CS WR k n n 0 1

53. Registers and Counters53 Writing RAM To write to this RAM, you need to: – Enable the chip by setting CS = 1. – Select the write operation, by setting WR = 1. – Send the desired address to the ADRS input. – Send the word to store to the DATA input. The output OUT is not needed for memory write operations. 2 k x n memory ADRSOUT DATA CS WR k n n 1 1

54. Registers and Counters54 Static memory How can you implement the memory chip? There are many different kinds of RAM. – We’ll start off discussing static memory, which is most commonly used in caches and video cards. – Later we mention a little about dynamic memory, which forms the bulk of a computer’s main memory. Static memory is modeled using one latch for each bit of storage. Why use latches instead of flip flops? – A latch can be made with only two NAND or two NOR gates, but a flip-flop requires at least twice that much hardware. – In general, smaller is faster, cheaper and requires less power. – The tradeoff is that getting the timing exactly right is a pain.

55. Registers and Counters55 Starting with latches To start, we can use one latch to store each bit. A one-bit RAM cell is shown here. Since this is just a one-bit memory, an ADRS input is not needed. Writing to the RAM cell: – When CS = 1 and WR = 1, the latch control input will be 1. – The DATA input is thus saved in the D latch. Reading from the RAM cell and maintaining the current contents: – When CS = 0 or when WR = 0, the latch control input is also 0, so the latch just maintains its present state. – The current latch contents will appear on OUT.

56. Registers and Counters56 My first RAM We can use these cells to make a 4 x 1 RAM. Since there are four words, ADRS is two bits. Each word is only one bit, so DATA and OUT are one bit each. Word selection is done with a decoder attached to the CS inputs of the RAM cells. Only one cell can be read or written at a time. Notice that the outputs are connected together with a single line!

57. Registers and Counters57 In normal practice, it’s bad to connect outputs together. If the outputs have different values, then a conflict arises. The standard way to “combine” outputs is to use OR gates or muxes. This can get expensive, with many wires and gates with large fan-ins. Connecting outputs together

58. Registers and Counters58 Those funny triangles The triangle represents a three-state buffer. Unlike regular logic gates, the output can be one of three different possibilities, as shown in the table. “Disconnected” means no output appears at all, in which case it’s safe to connect OUT to another output signal. The disconnected value is also sometimes called high impedance or Hi-Z.

59. Registers and Counters59 Connecting three-state buffers together You can connect several three-state buffer outputs together if you can guarantee that only one of them is enabled at any time. The easiest way to do this is to use a decoder! If the decoder is disabled, then all the three-state buffers will appear to be disconnected, and OUT will also appear disconnected. If the decoder is enabled, then exactly one of its outputs will be true, so only one of the tri-state buffers will be connected and produce an output. The net result is we can save some wire and gate costs. We also get a little more flexibility in putting circuits together.

60. Registers and Counters60 Bigger and better Here is the 4 x 1 RAM once again. How can we make a “wider” memory with more bits per word, like maybe a 4 x 4 RAM? Duplicate the stuff in the blue box!

61. Registers and Counters61 A 4 x 4 RAM DATA and OUT are now each four bits long, so you can read and write four-bit words.

62. Registers and Counters62 Bigger RAMs from smaller RAMs We can use small RAMs as building blocks for making larger memories, by following the same principles as in the previous examples. As an example, suppose we have some 64K x 8 RAMs to start with: – 64K = 2 6 x 2 10 = 2 16, so there are 16 address lines. – There are 8 data lines. 8 8 16

63. Registers and Counters63 8 8 16 Making a larger memory We can put four 64K x 8 chips together to make a 256K x 8 memory. For 256K words, we need 18 address lines. – The two most significant address lines go to the decoder, which selects one of the four 64K x 8 RAM chips. – The other 16 address lines are shared by the 64K x 8 chips. The 64K x 8 chips also share WR and DATA inputs. This assumes the 64K x 8 chips have three-state outputs.

64. Registers and Counters64 Analyzing the 256K x 8 RAM There are 256K words of memory, spread out among the four smaller 64K x 8 RAM chips. When the two most significant bits of the address are 00, the bottom RAM chip is selected. It holds data for the first 64K addresses. The next chip up is enabled when the address starts with 01. It holds data for the second 64K addresses. The third chip up holds data for the next 64K addresses. The final chip contains the data of the final 64K addresses. 8 8 16

65. Registers and Counters65 Address ranges 8 8 16 11 1111 1111 1111 1111 (0x3ffff)‏ to 11 0000 0000 0000 0000 (0x30000)‏ 10 1111 1111 1111 1111 (0x2ffff)‏ to 10 0000 0000 0000 0000 (0x20000)‏ 01 1111 1111 1111 1111 (0x1ffff)‏ to 01 0000 0000 0000 0000 (0x10000)‏ 00 1111 1111 1111 1111 (0x0ffff)‏ to 00 0000 0000 0000 0000 (0x00000)‏

66. Registers and Counters66 Making a wider memory You can also combine smaller chips to make wider memories, with the same number of addresses but more bits per word. Here is a 64K x 16 RAM, created from two 64K x 8 chips. – The left chip contains the most significant 8 bits of the data. – The right chip contains the lower 8 bits of the data. 16 88 88

67. Registers and Counters67 Getting to know Murphy “Early in the '50s, with the advent of jet aircraft there was a debate as to whether a pilot could safely eject from the aircraft. In order to find out whether a man could survive the stresses of ejection the Air Force undertook a study (USAF project MX981). The study involved shooting a rocket sled down a track, accelerating its passenger to speeds in excess of 630 miles of hour and then suddenly stopping in 1.4 seconds, generating over 40g's. One experiment involved a set of 16 accelerometers mounted in different parts of the subject's body. There were two ways each sensor could be glued to its mount. And of course, each was installed the wrong way! One of the engineers on the project, Edward A. Murphy, made the original pronouncement of Murphy's Law, "If there are two or more ways to do something, and one of those can result in catastrophe, then someone will do it." The test subject, Major John Paul's Stapp an Air Force flight surgeon leading the project, quoted Murphy in a press conference a few days later. Within months, Murphy's Law had spread to various technical cultures connected to aerospace engineering and finally to Webster's dictionary in 1958. “ excerpt taken from http://www.well.com/user/gjmurphy/Murphys_Law.html

68. Registers and Counters68 Error correction Murphy’s law: "If anything can go wrong, it will!" Memory is no exception! Some bit will flip once in a while.. Your task, of course if you accept it, is to – Detect whether there is an error – Correct it, if possible This slide will destroy itself in 5 seconds….

69. Registers and Counters69 Error-correction Use extra bits – For instance append a parity bit – For more interesting methods read the related section of the book.

70. Registers and Counters70 Summary A RAM looks like a bunch of registers connected together, allowing users to select a particular address to read or write. Much of the hardware in memory chips supports this selection process: – Chip select inputs – Decoders – Tri-state buffers By providing a general interface, it’s easy to connect RAMs together to make “longer” and “wider” memories.

71. Registers and Counters71 Other memories Some other kinds of memories. – Dynamic RAM is used for the bulk of computer memory. – Read-only memories and PLAs are two “programmable logic devices,” which can be considered as special types of memories.

72. Registers and Counters72 Dynamic memory in a nutshell Dynamic memory is built with capacitors. – A stored charge on the capacitor represents a logical 1. – No charge represents a logic 0. However, capacitors lose their charge after a few milliseconds. The memory requires constant refreshing to recharge the capacitors. (That’s what’s “dynamic” about it.) ‏ Dynamic RAMs tend to be physically smaller than static RAMs. – A single bit of data can be stored with just one capacitor and one transistor, while static RAM cells typically require 4-6 transistors. – This means dynamic RAM is cheaper and denser—more bits can be stored in the same physical area.

73. Registers and Counters73 SDRAM Synchronous DRAM, or SDRAM, is one of the most common types of PC memory now. Memory chips are organized into “modules” that are connected to the CPU via a 64-bit (8-byte) bus. Speeds are rated in megahertz: PC66, PC100 and PC133 memory run at 66MHz, 100MHz and 133MHz respectively. The memory bandwidth can be computed by multiplying the number of transfers per second by the size of each transfer. – PC100 can transfer up to 800MB per second (100MHz x 8 bytes/cycle). – PC133 can get over 1 GB per second. (from amazon.com) ‏

74. Registers and Counters74 DDR-RAM A newer type of memory is Double Data Rate, or DDR-RAM. It’s very similar to regular SDRAM, except data can be transferred on both the positive and negative clock edges. For 100-133MHz buses, the effective memory speeds appear to be 200-266MHz. This memory is confusingly called PC1600 and PC2100 RAM, because – 200MHz x 8 bytes/cycle = 1600MB/s – 266MHz x 8 bytes/cycle = 2100MB/s. DDR-RAM has lower power consumption, using 2.5V instead of 3.3V like SDRAM. This makes it good for notebooks and other mobile devices.

75. Registers and Counters75 RDRAM Another new type of memory called RDRAM is used in the Playstation 2 as well as some Pentium 4 computers. The data bus is only 16 bits wide. But the memory runs at 400MHz, and data can be transferred on both the positive and negative clock edges. – That works out to a maximum transfer rate of 1.6GB per second. – You can also implement two “channels” of memory, resulting in up to 3.2GB/s of bandwidth. (from amazon.com) ‏

76. Registers and Counters76 Dynamic vs. static memory In practice, dynamic RAM is used for a computer’s main memory, since it’s cheap and you can pack a lot of storage into a small space. – These days you can buy 2GB of memory for as little as 45TL. – You can also load a system with 8GB or more of memory. The disadvantage of dynamic RAM is its speed. – Transfer rates are 800MHz at best, which can be much slower than the processor itself. – You also have to consider latency, or the time it takes data to travel from RAM to the processor. Real systems augment dynamic memory with small but fast sections of static memory called caches. – Typical processor caches range in size from 2MB to 3MB. – That’s small compared to a 2GB main memory, but it’s enough to significantly increase a computer’s overall speed. – You’ll study caches later on in CENG331 next semester.

77. Registers and Counters77 Read-only memory A read-only memory, or ROM, is a special kind of memory whose contents cannot be easily modified. – The WR and DATA inputs that we saw in RAMs are not needed. – Data is stored onto a ROM chip using special hardware tools. ROMs are useful for holding data that never changes. – Arithmetic circuits might use tables to speed up computations of logarithms or divisions. – Many computers use a ROM to store important programs that should not be modified, such as the system BIOS. – PDAs, game machines, cell phones, vending machines and other electronic devices may also contain non-modifiable programs. 2 k x n ROM ADRSOUT CS kn

78. Registers and Counters78 Memories and functions ROMs are actually combinational devices, not sequential ones! – You can’t store arbitrary data into a ROM, so the same address will always contain the same data. – You can think of a ROM as a combinational circuit that takes an address as input, and produces some data as the output. A ROM table is basically just a truth table. – The table shows what data is stored at each ROM address. – You can generate that data combinationally, using the address as the input.

79. Registers and Counters79 Decoders We can already convert truth tables to circuits easily, with decoders. For example, you can think of this old circuit as a memory that “stores” the sum and carry outputs from the truth table on the right.

80. Registers and Counters80 ROM setup ROMs are based on this decoder implementation of functions. – A blank ROM just provides a decoder and several OR gates. – The connections between the decoder and the OR gates are “programmable,” so different functions can be implemented. To program a ROM, you just make the desired connections between the decoder outputs and the OR gate inputs.

81. Registers and Counters81 ROM example Here are three functions, V 2 V 1 V 0, implemented with an 8 x 3 ROM. Blue crosses (X) indicate connections between decoder outputs and OR gates. Otherwise there is no connection. V 2 =  m(1,2,3,4)V 1 =  m(2,6,7)V 0 =  m(4,6,7) ‏ A2A1A0A2A1A0

82. Registers and Counters82 V2V1V0V2V1V0 A2A1A0A2A1A0 The same example again Here is an alternative presentation of the same 8 x 3 ROM, using “abbreviated” OR gates to make the diagram neater. V 2 =  m(1,2,3,4) ‏ V 1 =  m(2,6,7) ‏ V 0 =  m(4,6,7) ‏

83. Registers and Counters83 Why is this a “memory”? This combinational circuit can be considered a read-only memory. – It stores eight words of data, each consisting of three bits. – The decoder inputs form an address, which refers to one of the eight available words. – So every input combination corresponds to an address, which is “read” to produce a 3-bit data output. V2V1V0V2V1V0 A2A1A0A2A1A0

84. Registers and Counters84 ROMs vs. RAMs There are some important differences between ROM and RAM. – ROMs are “non-volatile”—data is preserved even without power. On the other hand, RAM contents disappear once power is lost. – ROMs require special (and slower) techniques for writing, so they’re considered to be “read-only” devices. Some newer types of ROMs do allow for easier writing, although the speeds still don’t compare with regular RAMs. – MP3 players, digital cameras and other toys use CompactFlash, Secure Digital, or MemoryStick cards for non-volatile storage. – Many devices allow you to upgrade programs stored in “flash ROM.”

85. Registers and Counters85 Programmable logic arrays A ROM is potentially inefficient because it uses a decoder, which generates all possible minterms. No circuit minimization is done. Using a ROM to implement an n-input function requires: – An n-to-2 n decoder, with n inverters and 2 n n-input AND gates. – An OR gate with up to 2 n inputs. – The number of gates roughly doubles for each additional ROM input. A programmable logic array, or PLA, makes the decoder part of the ROM “programmable” too. Instead of generating all minterms, you can choose which products (not necessarily minterms) to generate.

86. Registers and Counters86 A blank 3 x 4 x 3 PLA This is a 3 x 4 x 3 PLA (3 inputs, up to 4 product terms, and 3 outputs), ready to be programmed. The left part of the diagram replaces the decoder used in a ROM. Connections can be made in the “AND array” to produce four arbitrary products, instead of 8 minterms as with a ROM. Those products can then be summed together in the “OR array.” Inputs Outputs AND array OR array

87. Registers and Counters87 Regular K-map minimization The normal K-map approach is to minimize the number of product terms for each individual function. For our three functions, this would result in a total of six different product terms. V2V1V0V2V1V0 V 2 =  m(1,2,3,4) ‏ V 1 =  m(2,6,7) ‏ V 0 =  m(4,6,7) ‏

88. Registers and Counters88 PLA minimization For a PLA, we should minimize the number of product terms for all functions together. We could express V 2, V 1 and V 0 with just four total products: V 2 = xy’z’ + x’z + x’yz’V 1 = x’yz’ + xyV 0 = xy’z’ + xy V 2 =  m(1,2,3,4) ‏ V 1 =  m(2,6,7) ‏ V 0 =  m(4,6,7) ‏

89. Registers and Counters89 PLA example So we can implement these three functions using a 3 x 4 x 3 PLA: V2V1V0V2V1V0 xy’z’ xy x’z x’yz’ V 2 =  m(1,2,3,4)= xy’z’ + x’z + x’yz’ V 1 =  m(2,6,7)= x’yz’ + xy V 0 =  m(4,6,7)= xy’z’ + xy A2A1A0A2A1A0

90. Registers and Counters90 PLA evaluation A k x m x n PLA can implement up to n functions of k inputs, each of which must be expressible with no more than m product terms. Unlike ROMs, PLAs allow you to choose which products are generated. – This can significantly reduce the fan-in (number of inputs) of gates, as well as the total number of gates. – However, a PLA is less general than a ROM. Not all functions may be expressible with the limited number of AND gates in a given PLA. In terms of memory, a k x m x n PLA has k address lines, and each of the 2 k addresses references an n-bit data value. But again, not all possible data values can be stored.

91. Registers and Counters91 Functions and memories ROMs and PLAs give us two more ways to implement functions. One difference between expressions/circuits and truth tables: – A circuit implies that some calculation has to be done on the inputs in order to arrive at the output. If the same inputs are given again, we have to repeat that calculation. – A truth table lists all possible combinations of inputs and their corresponding outputs. Instead of doing a potentially lengthy calculation, we can just “look up” the result of a function. The idea behind using a ROM or PLA to implement a function is to “store” the function’s truth table, so we don’t have to do any (well, very little) computation. This is like “memorization” or “caching” techniques in programming.

92. Registers and Counters92 Summary There are two main kinds of random access memory. – Static RAM costs more, but the memory is faster. Static RAM is often used to implement cache memories. – Dynamic RAM costs less and requires less physical space, making it ideal for larger-capacity memories. However, access times are also slower. ROMs and PLAs are programmable devices that can implement arbitrary functions, which is equivalent to acting as a read-only memory. – ROMs are simpler to program, but contain more gates. – PLAs use less hardware, but it requires some effort to minimize a set of functions. Also, the number of AND gates available can limit the number of expressible functions.