1. H-pT ASIC A.The logic of H-pT ASIC 1. overview 2. matrix, encoder, selector… B. Test result 1. verification 2. electrical characteristics C. Usage

2. HPT PS PP SL G-LINK Optical ASD LVDS Setting of High-pT ASIC and boards Block diagram of end-cap muon level-1 trigger system

3. 6 to 2 selector triplet-decoder doublet-decoder 6 to 2 selector delay controlH/L selector output A output B doublet in triplet in sub matrix unit High-pT ASIC Block Diagram Primary selector sub matrix unit encoder delay control

4. Primary selector sub matrix unit encoder doublet in triplet in 6 to 2 selector sub matrix unit Selecting highest 2 hits If the same pT, ASIC chooses upper one. Selecting the highest pT hit corresponding to centered one 6 to 2 sel H/L selector H/L Selector H has 1 st priority, pT is 2 nd priority. HHLL=HH HLL=HL LL=LL From HpT From LpT

5. 168421 +/- 44 22 11 for the wire/strip doublet input hit168421 for the wire triplet input hit8421 for the strip triplet input for example: 100110 = 7, 000000 = no hit, 111111 = 32(max), 100000 = 1(min) for example: 10111 = 8, 00000 = no hit, 11111 = 16(max), 10000 = 1(min) for example: 000000000 means no hit, 000001000 means pos = 0, pT = +0 Using 5 to 32bit decoder and 3 to 8bit decoder Using 4 to 16bit decoder Using 5 to 32bit decoder

6. oahloaid0oaid1oaid2oaposoasigoaq0oaq1oaq2oaq3 obhlobid0obid1obid2obposobsigobq0obq1obq2obq3 primary output secondary output 001 010 011 100 101 110 hit ID (oxid) 0101 position (oxpos) 000 = no hit 0 0000 0 0001 1 0001 0 0010 No hit = -1 = +1 = -2 = for example Output Data Format 1:HpT 0:LpT 54 0 0 60 doublet triplet

7. signal nameremarks dj Select JTAG / VME for delay setting : dj=1 is enabling JTAG control. orsw or function enable with orsw=0. This function is effect on strip mode. wors mode switch: working on wire mode with wors=0 and on strip mode with wors=1. invswDC balanced input mode on (invsw=1) rst_reset internal registers (rst_=0) dset delay data set by rising edge of iclk; this function is effect with dj=0 and dxr. ASIC Control Signal 000000101010101010 LVDS Serializerinvsw=1 ---0 110 1101 110 dset

8. Delay Control 3bit delay controlled by JTAG or VME This ASIC has 3bit X 7 delay for 7 blocks. @ 0.5CLK 2 way setting method of delay registers JTAG : dj=1, data from JTAG VME : dj=0, data from VME, set by dset From doublet From triplet wire mode

9. register nameinstruction code delay_block0 (d0r)0000100y delay_block1 (d1r)0001000y delay_block2 (d2r)0001100y delay_block3 (d3r)0010000y delay_block4 (d4r)0010100y delay_block5 (d5r)0011000y delay_block6 (d6r)0011100y g-link_control (3bit-reg)0100000y sample/preload00000010 extest00000000 bypass11111111 *r: 3bit register (r=a,b,c) *y: y=0(read)/1(write) JTAG Register y=0 mode will be used in read-back. TDITDO Delay Block2

10. All the registers of H-pT ASIC are voting structure MAJ XOR SEU OUT IN If there is a SEU on a register, we can detect with SEU-pin. 111 110 100 OUTSEU 1 1 0 0 1 1 example

11. Costs for mass-production of H-pT ASIC \2,550 = € 21.74 = 31.89CHF @chip Geometry Ball Grid Array 256-pins

12. Pin spec. of H-pT ASIC # of input pin 54 (doublet-in) 60 (triplet-in) 3 (TDI, TMS, TCK) 2 (clk, reset) 21 (delay control) 5 (inv, or, ws, dset, dj) total 145 # of output pin 10 (A-out) 10 (B-out) 1 (SEU) 1 (TDO) 3 (for g-link control) total 25

13. Test Result

14. Test Setup for verification test HPT Test Board TOM (FIFO) PPG50 (Pattern Gen) LVTTL PPG50 = pattern generator ROD = output-data storage PC = simulator and comparator PC Test bit- pattern compare

15. tracktest patternError 119,9680 2 0 314,7120 Matrix Verification Checking List wire tracktest patternError 119,9680 2 0 314,7120 strip Delay ASIC Control (dc, reset, or, w/s, dj, dset)

16. compare Test bit- pattern Trigger System Simulation Trigger System Hardware Test Setup for connection test JTAG Control Checking List

17. Timing Characteristics <1.0<1.0ns iclk Input data 32 < t d < 34 ns iclk Outgoing data data 33ns << 3clocks (TDR) setup/hold time typical delay

18. clock nameminimumtypicalmaximum system clock (iclk) -40.08MHz50MHz* jtag clock (tck)--20MHz -typical power consumption (40.08MHz) 148mW -minimumtypicalmaximum Supplied voltage 2.2V3.3V3.7V Electrical Characteristics * Limited by test system, PPG50

19. Board Design

20. EO- CONV G-LINK LVDS Rx HpT ASIC Optical OUT LVDS IN For the wire board EO- CONV G-LINK LVDS Rx HpT ASIC Optical OUT LVDS IN For the Strip board TC7MA157 FK H/LID POS+/-pT3pT2pT1pT0 if pT > 0, OUT = no hit Output Format

21. VME operation HPt ASIC G HPt ASIC G G HPt ASIC G HPt ASIC Clock, JTAG, and reset EWD 0 EWT 0 Optical Fiber Doublet 18-bit → serialized LVDS Triplet 18-bit → serialized LVDS 9U-VME BOARD High-pT Board (Endcap-Wire) Sector Logic EWT 5 EWT 6 EWD 7 EWD 8 EWD 9 EWD 1 EWD 2 EWD 3 EWT 1 EWT 2 EWD 4 EWD 5 EWD 6 EWT 3 EWT 4 Sector Logic Sector Logic Sector Logic LVDS Rx

22. VME operation HPt ASIC HPt ASIC HPt ASIC HPt ASIC Clock, JTAG, and reset Sector Logic Sector Logic Sector Logic LVDS Rx Optical Fiber Doublet 18-bit → serialized LVDS Triplet 2x20-bit → serialized LVDS High-pT Board (Endcap-Strip) EST1 EST0 ’ EST0 Sector Logic ESD3 ’ ESD4 ’ EST1 ’ ESD0 ‘ ESD1 ‘ ESD2 ‘ ESD3 ESD4 ESD0 ESD1 ESD2 9U-VME BOARD G G G G TC7MA157FK

23. VME operation HPt ASIC Clock, JTAG, and reset Sector Logic Sector Logic LVDS Rx Optical Fiber Doublet 18-bit → serialized LVDS Triplet 18/20-bit → serialized LVDS High-pT Board (Forward) FSD0 FST0 Sector Logic FWT0 FWT1 FWD3 FWD0 FWD1 FWD2 9U-VME BOARD HPt ASIC HPt ASIC FWT2 FWT3 HPt ASIC G G G TC7MA157FK

24. SUMMARY All the functions of H-pT ASIC have been verified. The electrical characteristics have been checked. We have designed 3 H-pT boards available