1. New Coil Drivers Time Line Alberto Gennai I.N.F.N. Pisa

2. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa2 Documentation Kit Final Design Description –VIR-SPE-PIS-4900-121, New Coil Drivers Final Design Schedule and Budget –VIR-SPE-PIS-4900-129, New Coil Drivers 2006 Budget Presentations to the Virgo Collaboration Detector Meeting 22/01/2004 Detector Meeting 08/06/2004 Detector Meeting 28/07/2004 Virgo R&D 30/09/2004 Detector Meeting 01/11/2004 Coil Drivers Meeting 10/01/2005 Electronic R&D Meeting 9/02/2006 Conferences –IEEE Workshop 21/11/2004 –Amaldi 6 Poster Session –Australia-Italy Workshop, 5/10/2005

3. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa3 Overview and Motivations Coil-magnet pair actuators steering VIRGO optical elements need a dynamical range wider than what initially foreseen due to the big force impulse required for acquiring the lock of VIRGO optical cavities.

4. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa4 Actuator noise: current status Overview and Motivations (cont.)

5. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa5 Extending Dynamics Solution –Use of 2 DAC channels DAC #1 for lock acquisition when the large force impulse is required (up to 2A output current) DAC #2 for linear regime when low noise is required (programmable max output current) Prototype currently in use

6. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa6 Requirements Specification de-emphasis filter with  p = 2  rad/sec and  z = 60  rad/sec

7. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa7 Prototypes Status Emphasys filter No smooth transition

8. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa8 Potential Risk Since ITF re-start problems were detected switching coil driver prototypes (lock lost when disconnecting HighPower section) Investigations are in progress to check prototypes behavior (V. Dattilo, M. Barsuglia). Report expected to be ready soon

9. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa9 Final Design – Standard Course Standard operation “2 steps” sequence will be the following 1.High Power and Low Noise #2 sections are both connected to coil. Low Noise #1 section is disconnected. Use Analog IN #1 and High Power section to acquire lock with Analog IN #2 set to zero. 2.Set Analog IN #1 to zero and Analog IN #2 to required correction signal. 3.Disconnect High Power section. 4.Connect Low Noise #1. 5.Set Analog IN #2 to zero and Analog IN #1 to required correction signal. 6.Disconnect Low Noise #2.

10. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa10 Final Design –Improved EMI/EMC To improve EMI/EMC, digital to analog and analog to digital converters, currently installed in VIRGO Data Acquisition room and connected to coil drivers with about 30 meters of STP cable, can be installed on-board

11. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa11 Final Design – Product Breakdown Each Coil Driver module is composed by two distinct sections: –ACDV. Analog part implementing the High Power section, the two Low Noise sections and the two monitoring sections. –DCDV. Digital part implementing the control interface of the CDV04 module for sections switch, gain selection and configuration. Development of this part (R&D Virgo Control System Upgrade) is in progress. Installation in Virgo foreseen to take place in 2008. CDV04 ACDV HighPower LowNoise #1 LowNoise #2 DCDV Relays Control ADC-DAC

12. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa12 ACDV Schedule: Main Milestones M1: July 14 (TBC) –Commissioning-Operation report ready –CRE approved (change was already approved in January 2005 in a dedicated meeting) M2: September 15th (M1 + 40 wrk days) –4 new prototypes (12 coils) ready to be installed for test (NE and/or WE?) M3: November (M2 + 50 wrk days) –Full production ready to be installed M4: 2007 (TBC) –Upper stage coil drivers production

13. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa13

14. Detector Meeting, 5/7/2006 A.Gennai, INFN Pisa14 Resources Roberto CavalieriE.G.O. Alberto GennaiI.N.F.N. Pisa Carlo MagazzùI.N.F.N. Pisa Federico PaolettiE.G.O. Diego PassuelloI.N.F.N. Pisa Ciro TremolaI.N.F.N. & University of Pisa