1. SVD DAQ Status Koji Hara (KEK) 2012/7/19 DAQ workshop1

2. SVD DAQ System Overview Analog APV25 readout is through copper cable to FADCs Junction box provides LV to front-end Sparsification and hit time finding is done in FADC modules Data is passed on through FTB to COPPER readout system FADC, FTB prototypes are being developed. 22012/7/19 DAQ workshop Front-end hybrids Rad-hard DC/DC converters Analog level translation, data sparsification and hit time reconstruction Unified Belle II DAQ system ~2m copper cable Junction box ~10m copper cable FADC+PROC C O P P E R Unified optical data link (>20m) Finesse Transmitter Board (FTB) 1748 APV25 chips

3. Front-End: New Hybrids New hybrids for L4,5,6 (forward side) Geometry, connector, mounting holes, chip positions according to overall SVD design 2 variants: – P-side: 4 APV25 chips – N-side: 6 APV25 chips Tested OK with chips Soon to be used for modules with sensors 2012/7/19 DAQ workshop3 M.Friedl

4. Junction Box Dock box contains 6 mother boards Shape will be similar to SVD2 DOCKs, but smaller and lighter to leave some space for shielding Detail design to be done DC/DC converters placed on the mother boards to provide LV to the front-end 2012/7/19 DAQ workshop4 M.Friedl

5. DC/DC Converter: Noise Comparison Same noise within measurement precision (few %) between conventional and DC/DC powering 2012/7/19 DAQ workshop5 1 and 2 bare hybrid boards (without sensors) attached for tests with 2m final cable M.Friedl

6. FADC Similar to SVD2 FADC, but with higher density and more powerful FPGA FPGA: Altera Stratix 4GX – basic firmware exists 48 APV inputs x 48 FADCs (24 inputs x 80 FADCs in TDR) Level translation boards have been produced Other parts are being designed – Several parts are ready 2012/7/19 DAQ workshop 6 Stratix 4GX daughter board VME Altera Level translation + data sparsification and hit timing reconstruction M.Friedl

7. FADC: Level Translation Tests 2012/7/19 DAQ workshop7  Both boards tested thoroughly, working perfectly fine  Short (2m) and long (12m) cable to FADC   100V between floating and GND sides  No damage with repeated instantaneous shorting of HV APVDAQ Repeater Ana+Digi daughter boards on adapter board APV25 Hybrid M.Friedl (HEPHY Vienna)

8. Finesse Transmitter Board (FTB) Sends FADC data through optical link to – COPPER – Pixel system Need to implement Belle2link on Spartan6 – Co-operating with IHEP 2012/7/19 DAQ workshop 8 Prototype:FTBfunctionality +tests possibility T. Saito, K. Hara, W. Ostrowicz

9. FTB Optical link test 2012/7/19 DAQ workshop9 Clock (127MHz) SP605 (reference) DATA FTB FTSW Stability of the FTB hardware Optical link quality using external clock from FTSW for Belle2Link have been checked Pseudo random bit stream data test with the PRBS-7 pattern have been performed for both TX and RX of FTB @ 3.175 Gbps, 1.588 Gbps FTB (TX generator)  SP605 (RX checker) SP605 (TX generator)  FTB (RX checker) (no error for SP605  SP605 for > 24 hours) Temperature monitor T. Saito, K. Hara, W. Ostrowicz

10. FTB Optical link test Result Two prototype boards are being tested – With different PCB materials (both were expected to work) FR-4 FR-408 (better performance but more expensive) FTB prototype with FR-4 @ 3.175 Gbps – FTB receiver : 842 errors in 93 hours  9 errors/hour error rate=1/10 12 bits – SP605 receiver : 96 errors in 93 hours  1 errors/hour error rate=1/10 13 bits @ 1.588 Gbps No error for 10 hours FTB prototype with FR-408 (still being tested) @ 3.175 Gbps No error for > 10 hours 2012/7/19 DAQ workshop10 FTB with FR-4 is not OK @ 3.175 Gbps (OK @ 1.588 Gbps) FTB with FR-408 is OK @ 3.175 Gbps FTB with FR-4 is not OK @ 3.175 Gbps (OK @ 1.588 Gbps) FTB with FR-408 is OK @ 3.175 Gbps

11. Summary & Outlook Front-end: – new hybrids – working fine Junction box: – DC/DC converters – working fine, no noise penalty – DOCK box to be designed FADC: – Level translation daughter boards – working fine – Other parts in progress – Firmware to be done once hardware is ready FTB: – Optical link with the external clock have been tested – Belle2link porting work is need to be done 2012/7/19 DAQ workshop11

12. Belle2Link porting work We agreed with Zhen-An (IHEP), Nakao-san that SVD group contribute to the porting work to Spartan6. How about to visit IHEP August 6-12 ? – K. Hara and T. Saito (Tohoku-U) are willing to do 2012/7/19 DAQ workshop12

13. 2012/7/19 DAQ workshop13

14. Junction Box: DOCK Arrangement Space for shielding 2012/7/19 DAQ workshop14 BackwardForward SVD PXD (PXD box is only a placeholder)