1. S!LK silk.kookmin.ac.kr Capstone Design Ⅰ 1. CMOS Inverter 2. SONOS Memory 2014. 3. 13 Dae Hwan Kim Jungmin Lee Seungguk Kim

2. CMOS Inverter Basic Theory

3. V DD S D B B S PMOS NMOS + V in - D + V out - CMOS inverter: Most basic element of digital static CMOS circuit Combination of an N-MOSFET and P-MOSFET One of the transistors is “ON” in the steady state, there is no static current or static power consumption. Power dissipation occurs only during switching transient when a charging or discharging current is flowing through the circuit. Drain terminal of nMOS and pMOS are common and connected to the output terminal. Source terminal of nMOS is connected to the ground. Source terminal of pMOS is connected to the V DD. Basic Theory

4. CMOS inverter I-V Characteristics: Case 1) V in = 0 V gsn = 0 → nMOS “OFF” V gsp = -V DD → pMOS “ON” ⇒ V out = V DD by current path through pMOS as a pull-up transistor Case 2) V in = V dd V gsn = V DD → nMOS “ON” V gsp = 0 → pMOS “OFF” ⇒ V out = 0 by current path through nMOS as a pull-down transistor One transistor is “ON”, there is no direct current from V DD to the GND ⇒ No static power consumption Basic Theory

5. CMOS Inverter Structure & Reference

6. CMOS Inverter (Reference) CMOS inverter : cross-sectional view & circuit (V DD = 1.2V, V IN = 0 ~ V DD ) n-type dopant : Arsenic p-type dopant : Boron

7. Geometric parameters Value L total [μm]1.1 L g [nm]65 L sp [μm]0.1 T ox [nm]1.5 H sub [μm]1 H pg [μm]0.2 X j,SD [μm]0.12 W n orW p [μm] 1 Process parameters Value N sub [cm -3 ]7x10 17 N pg [cm -3 ]1x10 20 N S or N D [cm -3 ]1x10 20 N halo [cm -3 ]3x10 17 3.9 (SiO 2 ) nMOS (pMOS) gate type n+ (p+) polysilicon nMOS (pMOS) source/drain type n+ (p+) polysilicon nMOS (pMOS) substrate type p (n) silicon *nMOSFET/pMOSFET/MOS-cap :  Type 을 제외한 모든 parameters 값은 같음  MOS-cap 은 nMOSFET type The other parameters Value V DD [V]1.2 C load [fF]2.1 C mos [fF]2.1 Reference Parameters

8. Parameter Variables VariablesReferenceData #1Data #2 N sub [cm -3 ] N pg [cm -3 ] X j,SD [nm]12060180 N halo [cm -3 ] T ox [nm]1.536 L g [nm]6540200 W n : W p 1 : 2.51 : 11 : 4 C load 1 × C MOS 0.1 × C MOS 10 × C MOS ε ox SiO 2 (3.9)HfO 2 (22)Si 3 N 4 (7.5) VariablesReferenceData #1Data #2 W n : W p 1 : 2.51 : 11 : 4 C load 1 × C MOS 0.1 × C MOS 10 × C MOS ε ox SiO 2 HfO 2 Si 3 N 4 Gate material (qφ m ) Polysilicon (nMOS : 4.05 pMOS : 5.16 ) nMOS : Molybdenum (4.53) pMOS : Copper (4.7) (C MOS = 2.1fF)

9. Electrical Parameters

10. Definition of Electrical Parameters From transfer curve (I DS -V GS )  Threshold voltage (V T )  The boundary of on/off switching in transistor  Subthreshold slope (SS)  The variation of gate bias needed for increase of 10 times drain current in subthreshold region  Off current (I off )  Drain current when V GS =0V  GIDL current (I GIDL ) (Gate-induced drain leakage current)  Drain current when V GS =-1V  On current (I on )  Drain current when V GS =V DD

11. Definition of Electrical Parameters What is DIBL?  Condition : -short channel length -High drain bias  The decrease of energy barrier in channel & source junction with the increase of drain bias  The increase of leakage current

12. What is GIDL current?  Condition : V GS 0  Leakage current of drain-substrate junction  Band-to-Band tunneling current of duplicated region of gate-drain Definition of Electrical Parameters

13. Circuit Performance Index (1) Voltage Transfer Characteristics

14. I DS V out V DD 0 III V IVII I PMOS V in =0 NMOS V in =V DD NMOS V in =0 PMOS V in =V DD I DN =I DP IV III IVII 0V TN V out V in V OH =V dd V OL = 0 V IL V IH V dd V dd - |V TP | V TN Slope = -1 nMOS sat. pMOS lin. Both sat. nMOS lin. pMOS sat. I II III IV V I= I P -I N V out point: intercept point of I P (V in )=I N (V in )  Operation mode I.nMOS cut-off 영역, pMOS linear 영역 II.nMOS saturation 영역, pMOS linear 영역 III.nMOS & pMOS saturation 영역 IV.nMOS linear 영역, pMOS saturation 영역 V.nMOS linear 영역, pMOS cut-off 영역 V in Voltage Transfer Characteristics (VTC) V dd - |V TP |

15. The ideal gate should have Infinite gain in the transition region Gate threshold located in the middle of logic swing High and low noise margins equal to half the swing Input and output impedances of infinity and zero, respectively g = -  V out V in R i =  R o = 0 Fanout =  NM H = NM L = V DD /2 Voltage Transfer Characteristics (VTC)

16.  Voltage gain : A V = (∂V out / ∂V in )  V out = V OUH (output high voltage) when (∂V out / ∂V in )= -1  V in = V IL (input low voltage) when (∂V out / ∂V in )= -1  V out = V OUL (output low voltage) when (∂V out / ∂V in )= -1  V in = V IH (input high voltage) when (∂V out / ∂V in )= -1  V S (switching voltage) when V in = V out  NM H = V OH - V IH : noise margin high  NM L = V IL - V OL : noise margin low V(x) V(y) Slope = -1 V OU H V OU L VILVIL VIHVIH VSVS V OH V OL Voltage Transfer Characteristics (VTC)

17. Large noise margins are desirable, but not sufficient requirement. Undefined region (forbidden) "1" "0" Gate output Gate input V OH V IL V OL V IH Noise margin high Noise margin low NM H = V OH - V IH NM L = V IL - V OL GND V DD GND Allowable noise level which does not hurt the logic operation. For robust circuits, want the “0” and “1” intervals to be as large as possible. Noise Margin

18. Circuit Performance Index (2) Delay Calculation

19. Delay Definition t V out V in t p = (t pHL + t pLH )/2 Propagation delay t 50% t pHL 50% t pLH tftf 90% 10% trtr Rising time V in V out Input signal Output signal 90% 10% Falling time

20. Propagation delay ① t pHL : pull-down delay time V in switches from 0 to V DD, V out decreases with time nMOS is at the saturation when V out changes from V DD to V DD /2 ② t pLH : pull-up delay time V in switches from V DD to 0, V out increases with time. pMOS is at the saturation when V out changes from 0 to V DD /2. Simple timing model Simple inverter model R eff ; effective on-resistance of transistor C L ; load capacitance Propagation delay Delay Calculation

21. Assumption ⇒ rising & falling time of input signal is zero. Average propagation delay Switching Time Analysis (1)

22. For deep submicron device, nMOS and pMOS remain in saturation region for all times during switching V DD → V DD /2 and V DD /2 → V DD, respectively. If we model a transistor as a resistor, t PHL = 0.69R N C L and t PLH = 0.69R P C L. Switching Time Analysis (2)

23. Circuit Performance Index (3) Power Consumption

24. ; Cannot be ignored in VLSI containing millions of transistors Power Dissipation (T. Sakurai, ISSCC2003) Power dissipation increases linearly with switching frequency. Due to the charging and discharging of capacitances Due to subthreshold leakage, pn junction leakage, etc Power Dissipation of CMOS VLSI

25. Total charge supplied by V DD and drained to GND ; Average current ; Dynamic (switching) Power (1)

26. Practical dynamic power is larger than Due to the short circuit power dissipation V DD -V T I short V in Dynamic (switching) power (2)

27. Critical in low-power battery-operated portable devices Sources of static power dissipation Subthreshold leakage Junction leakage DC current flow in ratioed logic such as pseudo-nMOS logic Subthreshold leakage can be reduced by Dynamically controlling V T ; by controlling the substrate bias, higher V T during standby and normal V T during normal operation Reduction of V DS during standby ; series transistor to the pull-up and pull-down paths for smaller V DS across each transistor, called source degeneration Static (standby) Power

28. TCAD simulation

29. n-MOSFET device structure n-MOSFET circuit :transfer curve p-MOSFET device structure p-MOSFET circuit :transfer curve MOSCAP structure Inverter circuit : VTC Inverter circuit : Transient curve TCAD simulation

30. tdr file MOSFET information (Ex : electric field, doping concentration, EBD, etc…) Structure file

31. <Electric field & mesh information> 2-D structure information

32. 1-D structure information Dimension cutting Doping concentration

33. 1-D structure information Electric field Energy band diagram

34. Data export

35. Data export Server connection  STDB folder  Saved folder  Data export to my computer

36. Homework

37. CMOS Inverter Example #1. N sub, L g variation 1. [Table #1] 에 주어진 공정변수 변화 (N sub, L g ) 에 따라 아래의 소자변수를 비교하고 이유에 대해 논하시오. (L g variation : short channel effect 관점 ) Process variations N sub [cm -3 ] Reference Data #1 Data #2 [Table #1] Process variations L g [nm] Reference Data #1 Data #2

38. CMOS Inverter (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교하고 이유에 대해 논하시오.

39. CMOS Inverter Example #2. N pg variation 1. [Table #2] 에 주어진 공정변수 변화 (N pg ) 에 따라 아래의 소자변수를 비교하고 이유에 대해 논하시오. (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static Process variations N pg [cm -3 ] Reference Data #1 Data #2 [Table #2] 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교, 설명하시오. (1) Threshold voltage (V T ) (2) Subthreshold slope (SS) (3) On current (I on ) (4) Off current (I off ) (5) GIDL current (I GIDL )

40. CMOS Inverter Example #3. X j,SD, L g variation (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static Process variations X j,SD [nm] Reference Data #160 Data #2180 [Table #3] 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교하고 이유에 대해 논하시오. 1. [Table #3] 에 주어진 공정변수 변화 (X j,SD, L g ) 에 따라 아래의 소자변수를 비교하고 이유에 대해 논하시오. (L g variation : short channel effect 관점 ) Process variations L g [nm] Reference Data #1 Data #2

41. CMOS Inverter Example #4. N halo, L g variation Process variations N halo [cm -3 ] Reference Data #10 (No halo) Data #2 [Table #4] 1. [Table #4] 에 주어진 공정변수 변화 (N halo, L g ) 에 따라 아래의 소자변수를 비교하고 이유에 대해 논하시오. (L g variation : short channel effect 관점 ) Process variations L g [nm] Reference Data #1 Data #2 (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교하고 이유에 대해 논하시오.

42. CMOS Inverter Example #5. T ox, L g variation Process variations T ox [nm] Reference Data #13 Data #26 [Table #5] 1. [Table #5] 에 주어진 공정변수 변화 (T ox, L g ) 에 따라 아래의 소자변수를 비교하고 이유에 대해 논하시오. (L g variation : short channel effect 관점 ) Process variations L g [nm] Reference Data #1 Data #2 (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교하고 이유에 대해 논하시오.

43. CMOS Inverter Example #6. W n : W p variation 1. [Table #6] 에 주어진 공정변수 변화 (W n : W p ) 에 따라 아래의 소자변수를 비교, 설명하시오. Process variations W n : W p Reference Data #11 : 1 Data #21 : 4 [Table #6] (1) Threshold voltage (V T ) (2) Subthreshold slope (SS) (3) On current (I on ) (4) Off current (I off ) (5) GIDL current(I GIDL ) (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교, 설명하시오.

44. CMOS Inverter Example #7. C load variation Process variations C load Reference Data #10.1 × C MOS Data #210 × C MOS [Table #7] 1. [Table #7] 에 주어진 공정변수 변화 (C load ) 에 따라 아래의 소자변수를 비교, 설명하시오. (1) Threshold voltage (V T ) (2) Subthreshold slope (SS) (3) On current (I on ) (4) Off current (I off ) (5) GIDL current(I GIDL ) (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교, 설명하시오. (C MOS = 2.1fF)

45. CMOS Inverter Example #8. ε ox variation Process variations Oxide material ( ε ox ) ReferenceSiO 2 (3.9) Data #1HfO 2 (22) Data #2Si 3 N 4 (7.5) [Table #8] 1. [Table #8] 에 주어진 공정변수 변화 (ε ox ) 에 따라 아래의 소자변수를 비교, 설명하시오. (1) Threshold voltage (V T ) (2) Subthreshold slope (SS) (3) On current (I on ) (4) Off current (I off ) (5) GIDL current(I GIDL ) (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교, 설명하시오.

46. CMOS Inverter Example #9. qφ m variation Process variations qφmqφm Reference nMOS : Polysilicon (4.05) pMOS : Polysilicon (5.16) Data nMOS : Molybdenum (4.53) pMOS : Copper (4.7) [Table #9] 1. [Table #9] 에 주어진 공정변수 변화 ( qφ m ) 에 따라 아래의 소자변수를 비교, 설명하시오. (1) Threshold voltage (V T ) (2) Subthreshold slope (SS) (3) On current (I on ) (4) Off current (I off ) (5) GIDL current(I GIDL ) (1) Noise margin (NM) - V IL, V IH, NM L, NM H (2) Propagation delay - t pHL, t pLH, t p, t f, t r (3) Power consumption - P dynamic, P static 2. 소자변수 변화의 관점에서 아래의 회로 성능지수를 비교, 설명하시오.