1. ASIC development for SiPM readout F. Corsi, M. Foresta, C. Marzocca, G. Matarrese DEE - Politecnico di Bari and INFN-Sezione di Bari, Italy on behalf of DASIPM2 collaboration Pixel 2008 International Workshop – Fermilab, Batavia

2. Modelling of the SiPM and parameter extraction procedure Front-end architecture and first measurement results Design and characterization of a first version of the analog channel Architecture and design of a 8 channel prototype Future work Agenda

3. Electrical model of a SiPM R q : quenching resistor (hundreds of k  ) C d : photodiode capacitance (few tens of fF) C q : parasitic capacitance in parallel to R q (smaller than C d ) I AV : current source modelling the total charge delivered by a microcell during the avalanche  C g : parasitic capacitance due to the routing of the bias voltage to the N microcells, realized with a metal grid. Example: metal-substrate unit area capacitance 0.03 fF/mm2 metal grid = 35% of the total detector area = 1mm2  Avalanche time constants much faster than those introduced by the circuit: I AV can be approximated as a short pulse containing the total amount of charge delivered by the firing microcell Q=  V(C d +C q ), with  V=V BIAS -V BR Cg  10pF, without considering the fringe parasitics

4. Parameter extraction procedure I R q : forward characteristic of the SiPM,  V/  I is almost constant and equal to R q /N _____ Measured characteristic _____ Least square linear fit Forward characteristic of a SiPM produced by FBK-Irst. Slope = 1.59 mS R q /N = 629  N = 625 R q = 393 k  V bias [V] Q [C] * Measured points __ Least square linear fit Charge contained in a single dark count pulse vs. bias voltage Cd+Cq: charge associated to a single dark pulse as a function of the bias voltage: Q=(C d +C q )(V bias -V br )

5. Parameter extraction procedure II  CV plotter measurements of the SiPM near the breakdown voltage: Y M and C M  According to the SiPM model, Y M and C M are expressed in terms of C dtot =NC d, C qtot =NC q, R qtot =R q /N and the frequency  of the signal used by the CV plotter. YMYM CMCM C qtot CgCg C dtot R qtot Y M [  S] C M [pF] V bias [V] CV plotter measurement results for the device from FBK-Irst. C d,C q CgCg

6. Results of the extraction procedure  Extraction procedure applied to two SiPM detectors from different manufacturers.  The table summarizes the main features of the devices and the results obtained. Model ParameterSiPM FBK-Irst N=625, Vbias=35V SiPM Photonique N=516, Vbias=63V RqRq 393 kΩ774 kΩ V br 31.2 V61 V Q175.5 fC127.1 fC CdCd 34.6 fF40.8 fF CqCq 12.2 fF21.2 fF CgCg 27.8 pF18.1 pF

7. Front-end electronics: different approaches RSRS SiPM Vbias ISIS k I S = I OUT Charge sensitive amplifierVoltage amplifierCurrent amplifier - + SiPM Vbias CFCF V OUT + - RSRS SiPM Vbias V OUT A I-V conversion is realized by means of R S The value of R S affects the gain and the signal waveform V OUT must be integrated to extract the charge information: thus a further V-I conversion is needed R S is the (small) input impedance of the current buffer The output current can be easily replicated (by means of current mirrors) and further processed (e.g. integrated) The circuit is inherently fast Less problems of dynamic range The charge Q delivered by the detector is collected on C F If the maximum  V OUT is 3V and Q is 50pC (about 300 SiPM microcells), C F must be 16.7pF Perspective limitations in dynamic range, die area, power consumption

8. SiPM + front-end behaviour CqCq A) SiPM coupled to an amplifier with input impedance R s An analytical study of the circuit can be carried out with reference to the simplified schematic depicted below. The two circuits give very similar results, provided that R s is much lower than R qtot =R q /N I AV RqRq CdCd (N-1)C d (N-1)C q R q /(N-1) CgCg RSRS - V IN I IN + I AV RqRq CdCd CqCq IqIq IqIq CgCg C eq - V IN + I IN RSRS B) Simplified circuit

9. SiPM + front-end behaviour Time V IN Response of the circuits A) and B) to a single dark pulse (160fC) for three different values of Rs and typical parameter values The simplified circuit B) has two time constants:  IN = R s C tot  r =R q (C d +C q ) The peak of V IN is almost independent of R s A constant fraction Q IN of the charge Q delivered during the avalanche is almost instantly collected on C tot =C g +C eq R s =75  R s =50  R s =20  _____ Circuit A) _____ Circuit B)

10. Bandwidth of the amplifier Amplifier output voltage for a single dark pulse: same gain and different bandwidth _____ BW=500MHz _____ BW=100MHz Time V OUT R s =20  _____ BW=500MHz _____ BW=100MHz Time V OUT R s =75  The bandwidth of the amplifier directly affects the rise time of the waveform, independently of the value of R S The peak of the waveform is strongly dependent on the amplifier bandwidth, especially for low values of R S The time needed to collect the charge is just slightly influenced by the amplifier bandwidth The same conclusions are valid also for the waveform of the output current obtained with a current amplifier

11. Experimental validation of the model Two different amplifiers have been used to read-out the FBK-irst SiPM a) Transimpedance amplifier BW=80MHz Rs=110  Gain=2.7k  b) Voltage amplifier BW=360MHz Rs=50  Gain=140 The model extracted according to the procedure described above has been used in the SPICE simulations The fitting between simulations and measurements is quite good

12. Main simulated specs  Small signal bandwidth: 250MHz  Input resistance: 17   Total current consumption: 800uA  Linearity dynamic range: about 50pC  Rise time of the output waveform: 400ps  3.3V power supply  Vrif variable in the range 1V÷2V Experimental setup The CMOS current buffer  0.35  m standard CMOS technology  Common gate configuration (M1)  Feedback applied to increase bandwidth and decrease input resistance (M3, M2)  SiPM bias (and gain) fine tuning possible by varying Vrif 

13. Experimental setup 7V Experimental setup: blue LED light source Picture of the setupSingle dark pulse measurement (V br =-30.5V; V bias =-32.5V) The circuit has been coupled to a SiPM realized by FBK-Irst Blue Led I out 50Ω Pulse Generator Current Buffer Voltage Amplifier BNC SiPM R IV

14. Experimental setup 7V Dark pulse measurements Charge measurements at V bias = -32.5V Comparison with a very fast discrete voltage amplifier front-end, used as a reference: Average dark pulse charge Integrated current buffer: 143fC Discrete voltage amplifier: 142fC The standard deviation is worse:  int  2  disc

15. Experimental setup Dark pulse measurements Single dark pulse charge as a function of V bias

16. Blue LED measurements Average number of fired microcells as a function of the input pulse width

17. Experimental setup 7V Blue LED measurements Charge distribution for a 8.25ns input pulse width (in terms of no. of fired microcells) Comparison with the ref. amplifier : Average no. of fired microcells Current buffer: 39 Ref. amplifier: 38.4 Standard deviation Current buffer: 7.5 Ref. Amplifier: 7.2

18. Architecture of the analog channel

19. Main features  Variable gain integrator: Gain: 1V/pC  0.33V/pC (2 bits);  f = 200ns; Output voltage range: 0.3V ÷ 2.7V; Current mirror scaling factor 10:1  Current discriminator: Circuit structure similar to the one used for the pixels in ALICE Current mirror scaling factor 1:1; Threshold variable from 0 to 40µA (about 50 microcells @ V BIAS =-31.5V);  Baseline holder (Vbl=300mV): Very slow time constant; Non-linearities added to prevent baseline shifts at increasing event rates  Bias circuit added, based on a bandgap reference

20. Charge measurements (blue LED light source) Ouput voltage vs pulse width for different gain settings Typical output waveforms (Vbias=31.5V, pulse width=11.5ns)

21. Charge measurements (blue LED light source) From the previous characterization measurements we have: For pulse width = 9ns, n=115 fired microcells  If Vbias = 31.5 V, the total injected charge is Q T = Q µcell (31.5V)*n = 6.9pC If Vbias = 32.5 V, the total injected charge is Q T = Q µcell (32.5V)*n = 17.3pC Vbias31.5V32.5V Q T /(M*C f )690mV1.73V V peak -V bl 670mV1.76V Measurement are in good agreement with the expected results

22. Current discriminator output: jitter measurements Jitter measurements for the electronics alone and the electronics coupled to the LED-SiPM system

23. It is based on a P-MOS current mirror as a rectifying element Design of the 8 channel ASIC: the Peak Detector (PD) I BIAS added to improve the speed of operation, especially for small signals OTA _ + Integrator output out I BIAS V DISC C hold =2pF reset V DD M1M1 M2M2 MRMR

24. Experimental setup PD: simulation resullts Simulations show that the PD is able to follow the integrator output and to hold its peak

25. config_reg DAC Vrif DAC I_th MUX_reg Trig. reg. CSA Curbuf PD Curdisc CSA Curbuf PD Curdisc CSA Curbuf PD Curdisc MUX ADC Read_out logic srq_pad MUX_sel Vrif Architecture of the test chip F_or reset_pad ck_pad rw_pad data_pad gain ch_0 ch_1 ch_7 gain I_thVrif I_thVrif gain I_thVrif gain EOC ADC_ck a_out_0 a_out_1 a_out_7 trig_0 trig_1 trig_7 I_th data Ext. bias Ext. bias Ext. bias

26. Experimental setup Main features of the test chip Three operating modes: write configuration, read configuration and acquisition Two acquisition modes: “sparse read-out” and “serial read-out” All the channels share the same Vrif e I_th 8 bit successive approximation ADC from a library Fast-OR circuit operating in current mode, to improve the speed of operation

27. Read-out procedure for the test chip A)An event activates the SRQ bus (by default at Hi-Z) B)FPGA gives a time-stamp to the event and takes control of the SRQ bus during the read-out procedure C)SRQ, in its active state, is used to “freeze” the content of the trigger registers (no more trigger are accepted) D)FPGA waits the time needed by the PDs to reach the peak and sends the CLOCK signal to the ASICs F)The read-out logic starts the A/D conversions and sends the results to FPGA on the DATA_i pad G)When all the conversions have been completed, FPGA releases the SRQ bus and sends a RESET signal

28. Layout of the test chip

29. Characterization of the 8-channel ASIC Revision of the read-out procedure according to a target application (small animal PET) Design of a fast on-chip ADC Design of a 32-channel ASIC to be coupled to 2x8 SiPM matrices from FBK-Irst Migration to another technology (for instance 0.18um) Measure Future work