1. CBM 12 th Meeting, October 14-18, 2008, Dubna Present status of the first version of NIHAM TRD-FEE analogic CHIP Vasile Catanescu and Mihai Petrovici NIHAM - Bucharest N I H A M HPD

2. Summary: 1. Introduction: The first NIHAM chip for a HCR TRD Goals 2. Specifications of the NIHAM first version analog FEE for HCR TRD 3. Some new features, specific to a fast analog channel, implemented into the chip 4. Additional, in chip implemented circuits 5. Conclusions

3. 1. Introduction

4. HCRTRD - prototypes 1 GeV/c U A = 1900 V Xe,CO 2 (15%) Rohacell 5.1 %  4.3 %1.2 %  6.1 %  1800 V, foils, ~ 0.7 %  rejection 20/500/120  20/200/220, 1.4 better 1 st – single sided2 nd – double sided

5. Real Size Prototype

6. Three layers per TRD station

7. Single cell

8. Readout Pad Plane Electrode

9. - the chip is developed in AMS 0.35µm technology - acts as an analog front end electronics for HCR TRD

10. Number of analog channels: 8 Analog channel outputs: a) fast semi Gaussian output signal b) peak sense output signal 2. Specifications of the NIHAM first version analog FEE for HCR TRD

11. ● Average pulse rate: over 300 kcps ● Detector capacitance: 25 pF ● Input charge range: 0.15 fC…165 fC ● Input type: DC single ended ● Channel gain: 6.1 mV/fC ● Shaping time: 20 ns or 40 ns ( 1 bit select)‏ ● Output pulse FWHM: 65 ns or 120 ns ● Output type: single ended ‏ ● Output voltage swing: 0…..+1V ● Output DC voltage level: 0.2V…..1V (cont. adj.)‏ ● Output pulse variations: - with Temp=0…..70 °C < 1.7% (0.025%/ °C)‏ - with Vdda=3.0…..3.6V < 0.03% ● Output base line shift: - with Temp=0…..70 °C < 17µV/ °C - with Vdda=3.0…..3.6V <0.22% - with leakage current < 7µV/nA ● Channel ENC: < 900e (Cd=25pF & shaping time 40ns)‏ ● Integral nonlinearity: <0.6% ● Overshoot(undershoot): <0.8% ● Threshold ( variable): 0…..165 fC (full range), cont.adj. ● Hit occurance signal: logic level ● Input/Output interface: transfer on request/grant basis ● In chip pulse generator: for testing channel gain ● Power consumption: about 11mW/ch 2.1 ASIC analog channels, main specifications

12. 3. Some new features, specific to a fast analog channel, implemented into the chip 3.1 Typical response of analog channel to slow or moderate counting rate ● Analog channel signals: - preamplifier output - pole-zero circuit output - first shaper output - second shaper output ● Analog channel output to double pusle - first pulse of maximum amplitude - second pulse of 20% of maximum amplitude - delay between pulses = 1 microsecond

13. 3. Some new features, specific to fast analog channel, implemented into the chip (continued)‏ 3.2 Good response to double pulses and to high rate pulse ● Channel response without fast recovery circuits: - channel is dead for long time - double pulse separation and response to high rate pulses are not possible - important base line perturbations ● Channel response with fast recovery circuits: - short channel dead time even for large overload (ten times full range)‏ - very good double pulse separation and response to high pulse rate - no base line perturbations 3.3 Fast recovery to charge overload

14. 3. Some new features, specific to fast analog channel, implemented into the chip (continued)‏ 3.4 Baseline stabilization to the detector leakage current and/or high counting rate ● Analog channel without base line restoration: - large baseline shift IlkVDC(”/fast-out”)‏ -50nA141.3mV -25nA161mV 0nA180.6mV 25nA200.2mV 50nA219.9mV ● Analog channel with baseline restoration: - non significant base line shift IlkVDC(”/fast-out”)‏ -50nA201.3mV -25nA201.5mV 0nA201.6mV 25nA201.8mV 50nA202mV

15. 3. Some new features, specific to fast analog channel, implemented into the chip (continued)‏ 3.5 Shaping time selection ● Two shaping time option: 20ns and 40ns ● Logic level selection

16. Fast semigaussian output & puls peak sense circuit Variable threshold for selection of the useful peaks Over the threshold event signal 3. Some new features, specific to fast analog channel, implemented into the chip (continued)‏ 3.6 Fast track and pulse peak sense circuits and corresponding output signals.

17. 3.6 Fast track and pulse peak sense circuits and corresponding output signals. ● Fast linear gate and pulse peak sense citcuits ● Variable threshold for selection of the useful peaks 3. Some new features, specific to fast analog channel, implemented into the chip (continued)‏

18. 4. Additional in chip implemented circuits 4.1 Calibration pulse generator improved version of the ALICE TRD test pulse generator - Useful in finding channel gain - No additional software needed for gain finding

19. 4.2 Fast input/output interface for data processing 4. Additional in chip implemented circuits (continued)

20. Front-end electronics (FEE) CHIP’s one channel complete layout 0.2 x 2.15 mm 2

21. N IHAM B onding F acility

22. 5. Conclusions 5.1 Main desirable features were implemented to the chip ● Good response to double pulse ● Good response to high pulse rate ● Fast recovery from overload ● Immunity to detector leakage current ● Stable baseline to leakage current, temperature and voltage supplies variations ● More analog signal processing ● More generated timing signals 5.2 Outlook ● Submit to AMS the first version of HPD chip for high counting rate nuclear signal detectors Releasing of the new FEE board based on the ASIC developed for testing the HPD fast counting rate signal detectors. ToT version