1. Electronics Workshop GlueX Collaboration Meeting 28 March 2007 Fast Electronics R. Chris Cuevas Group Leader Jefferson Lab Physics Division Topics: Review the “Electronics Plan” JLAB F1TDC modification requirements fADC250 Update Energy Summing/Track Counts Global Clock/Trigger/Synchronization system

2. “The Electronics Plan” GlueX- Doc - 614

3. JLAB F1TDC Modification Requests Provide test pulse output signal on the unused 17th pair 4 outputs total,,, F1TDC has four input cables Add external RAM for event ‘blocking’ on board. Present design manages the event block mode with FPGA resources. Modify input circuits to receive LVDS signal levels from detector preamplifiers. (Or discriminators) Use Dpack or other solution for voltage regulator. (This is not a significant problem now, but the regulator tab is not secured to the board)

4. JLAB fADC-250 Update Milestones presented at the October 2006 GlueX collaboration meeting: October 2006 -- Design Complete [ Schematic reviewed] November ‘06 - February 2007 – Final layout/Routing/Review/Order March 2007 – Six (6) un-populated boards due March 30!!!. April 2007 – Two (2) boards will be sent for assembly April - May 2007 -- Functional testing and design verification June - July 2007 -- Summing data transfer tests with crate sum board August - Sept 2007 -- Continue testing with multiple boards, CODA test stand development,,,

5. Projects 1 3 2 Figure A Flash ADC, Energy Sum & Track Counts

6. For Detectors that do not produce an ‘Energy Sum”, can use the Hit Bits as the “Track Count” information?? This information would be transferred to the energy sum card and then to the Level 1 Trigger

7. Significant design challenges ADCs have extremely low jitter specifications Need to formulate reasonable design requirements now Clock management/fanout chips available with <1ps jitter,,, Fiber optic distribution from trigger to readout crates? What is the budget projected for this system? Use design resources from Accelerator RF group? (Master Oscillator distribution system) Non-VXS crates will need P2 interface design similar to Jlab F1TDC clock distribution ‘Hub’. Global Clock Timing/Trigger/Sync Distribution System