1. Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 20: October 25, 2010 Pass Transistors Synchronous Circuits

2. Today Pass Transistor Logic –Power –Tristates Clocking –Latches –Registers –Timing discipline Penn ESE370 Fall2010 -- DeHon 2

3. Pass Transistor Circuits Penn ESE370 Fall2010 -- DeHon 3

4. Power Implications What’s the power impact of partial swing? Penn ESE370 Fall2010 -- DeHon 4

5. Back to Rail How make it go to rail? Penn ESE370 Fall2010 -- DeHon 5

6. Transmission Gate Penn ESE370 Fall2010 -- DeHon 6

7. Level Restorer Penn ESE370 Fall2010 -- DeHon 7

8. Level Restorer Penn ESE370 Fall2010 -- DeHon 8

9. Level Restore What issue arises here? Penn ESE370 Fall2010 -- DeHon 9

10. Level Restore What issue arises here? Penn ESE370 Fall2010 -- DeHon 10

11. Tristate Sometimes want to be able to not drive a line –Bus driven from different places –I/O port – sometimes read, sometime write Penn ESE370 Fall2010 -- DeHon 11

12. Tristate Driver Penn ESE370 Fall2010 -- DeHon 12

13. Tri-State Drivers

14. Clocking Latches, Registers Penn ESE370 Fall2010 -- DeHon 14

15. Why Clocked Circuits? Synchronize external events Reuse logic –FSM –Pipelining Synchronize internal use of logic Penn ESE370 Fall2010 -- DeHon 15

16. Challenge Logic paths have different delays –E.g. different output bits in an adder Delay of signal data dependent –E.g. length of carry Delay is chip dependent –E.g. Threshold Variation Delay is environment dependent –E.g. Temperature Penn ESE370 Fall2010 -- DeHon 16

17. Challenge Logic paths have different delays Delay of signal data dependent Delay is chip dependent Delay is environment dependent Proper behavior depends on inputs being coordinated –Match the inputs that should interact Penn ESE370 Fall2010 -- DeHon 17

18. Discipline Add circuit elements to –hold values –and change at coordinated point Control when changes seen by circuit Only have to make sure to wait long enough for all results Decouple –timing of signal change –from timing of signal usage Penn ESE370 Fall2010 -- DeHon 18

19. Synchronous Discipline Add state elements (registers, latches) Compute –From state elements –Through combinational logic –To new values for state elements Penn ESE370 Fall2010 -- DeHon 19

20. What does this do? Penn ESE370 Fall2010 -- DeHon 20

21. Latch  =0  Out=In  =1  Out=Out  transitions 0  1 Out holds value Penn ESE370 Fall2010 -- DeHon 21

22. Latch In pass-through mode (  =0), –acts like buffer In latch mode (  =1), –holds last value given Penn ESE370 Fall2010 -- DeHon 22

23. Latch In pass-through mode (  =0), –acts like buffer In latch mode (  =1), –holds last value given Timing Requirements? Penn ESE370 Fall2010 -- DeHon 23

24. Latch Timing Must present input value sufficiently before the  transitions 0  1 –Must have time to propagate and charge Out Setup Time (t su ) – must setup latch input prior to pass  hold transition Penn ESE370 Fall2010 -- DeHon 24

25. Latch Timing Must not change input before switched over to hold state –Takes time for inverter to charge before hold path enabled. Penn ESE370 Fall2010 -- DeHon 25

26. Latch Timing Must not change input before switched over to hold state Hold Time (t hold )– must hold data input until pass  hold transition complete Penn ESE370 Fall2010 -- DeHon 26

27. What happens here? Penn ESE370 Fall2010 -- DeHon 27

28. Observe Latch alone –In flow-through mode half of cycle –Can still get flow-through, combinational cycles Penn ESE370 Fall2010 -- DeHon 28

29. Multiple Latch Discipline Open latches at disjoint times At all times one latch on every path is closed Penn ESE370 Fall2010 -- DeHon 29

30. Register Two back-to-back latches –Open one latch at a time –Having one of each on every cycle breaks up combinational cycle Penn ESE370 Fall2010 -- DeHon 30

31. Register Pass  hold on input latch samples value Hold  pass on output latch presents stored value to circuit Penn ESE370 Fall2010 -- DeHon 31 Master and Slave latches

32. Class ended here Penn ESE370 Fall2010 -- DeHon 32

33. Register How long from  1 rise to output? –At least part of clk  output (t clk-q ) Penn ESE370 Fall2010 -- DeHon 33

34. Clock Signal Can we use a single signal for clock? Penn ESE370 Fall2010 -- DeHon 34

35. Clock Issues Possible failure modes? –Flow through during transition? –Loading on clock phases –Delay in compute  1 ? Penn ESE370 Fall2010 -- DeHon 35

36. Appropriate Delay Creates non-overlap Too much could allow flow through Penn ESE370 Fall2010 -- DeHon 36

37. Clocking Discipline Penn ESE370 Fall2010 -- DeHon 37

38. Clocking Discipline Follow discipline of combinational logic broken by registers Compute –From state elements –Through combinational logic –To new values for state elements As long as clock cycle long enough, –Will get correct behavior Penn ESE370 Fall2010 -- DeHon 38

39. This Week Review tonight 7:30pm Midterm Wednesday –No lecture –Midterm 7-9pm in this room New homework out Thursday –Due Wed. next week Class Friday Penn ESE370 Fall2010 -- DeHon 39

40. Ideas Synchronize circuits –to external events –disciplined reuse of circuitry Leads to clocked circuit discipline –Uses state holding element –Prevents Combinational loops Timing assumptions (More) complex reasoning about all possible timings Penn ESE370 Fall2010 -- DeHon 40