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A 280mV-to-1.1V 256b Reconfigurable SIMD Vector Permutation Engine with 2-D Shuffle in 22nm CMOS [ISSCC ’12] Literature Review Fang-Li Yuan Advisor: Prof.

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Presentation on theme: "A 280mV-to-1.1V 256b Reconfigurable SIMD Vector Permutation Engine with 2-D Shuffle in 22nm CMOS [ISSCC ’12] Literature Review Fang-Li Yuan Advisor: Prof."— Presentation transcript:

1 A 280mV-to-1.1V 256b Reconfigurable SIMD Vector Permutation Engine with 2-D Shuffle in 22nm CMOS [ISSCC ’12] Literature Review Fang-Li Yuan Advisor: Prof. Dejan Marković 03/23/2012

2 IC Design Challenges: 1980s – Present  Session 1.4: Sustainability in Silicon & System Development – 1980s: Design productivity – 1990s: Power dissipation – 2000s: Leakage power – 2010s: 2 Fang-Li Yuan Moore’s Law continues to provide more transistors Energy Efficiency Power budgets limit our ability to use them

3 Intel’s Solutions – From Transistors to Circuits 3 Fang-Li Yuan 2007 ISSCC 2012 ISSCC

4 Near-Vth Computing: Great for Energy Efficiency 4 Fang-Li Yuan

5 IA-32: 1 st NTV Processor in 32nm CMOS 5 Fang-Li Yuan

6 NTV Circuits Gain 7x Efficiency in VPFP Mult-Add 6 Fang-Li Yuan

7 1 st NTV SIMD Engine in 22nm Tri-Gate Technology 7 Fang-Li Yuan

8 System-Level Overview 8 Fang-Li Yuan

9 Example: 64b 4x4 Matrix Transpose 9 Fang-Li Yuan

10 RF with PVT-tolerant Techniques & Vector FFs 10 Fang-Li Yuan

11 250mV Vmin Reduction Across PVT Variations 11 Fang-Li Yuan

12 Vector FFs Reduce Hold-Time Violations @ Low V 12 Fang-Li Yuan

13 ULVS LS, & Interleaved Folded Crossbar Layout 13 Fang-Li Yuan

14 ULVS Improves Vmin by 125mV 14 Fang-Li Yuan

15 RF and Logic Co-optimization: Iso-Vmin 15 Fang-Li Yuan

16 Measured Performance 16 Fang-Li Yuan

17 Conclusions  NTV computing is energy efficient but sensitive to PVT variation  Static ckts (e.g. RF read): better than dynamic ckts @ NTV  Shared P/N DETG writes improve V min across PVT variations  Vector FF/Mux share transistors across gates, averaging variation  ULVS LS interrupts contention devices, improving V min & power  Byte-wise enable-signal gating reduces power  Folded layout has 50% reduction in critical wiring length  Interleaved, opposite-direction data wires achieve 50% lower line-to-line coupling, improving SI & delay 17 Fang-Li Yuan

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