CSE477 L21 Multiplier Design.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 21: Multiplier Design Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

CSE477 L21 Multiplier Design.2Irwin&Vijay, PSU, 2002 Review: Basic Building Blocks  Datapath l Execution units -Adder, multiplier, divider, shifter, etc. l Register file and pipeline registers l Multiplexers, decoders  Control l Finite state machines (PLA, ROM, random logic)  Interconnect l Switches, arbiters, buses  Memory l Caches (SRAMs), TLBs, DRAMs, buffers

CSE477 L21 Multiplier Design.3Irwin&Vijay, PSU, 2002 Review: Binary Adder Landscape synchronous word parallel adders ripple carry adders (RCA) carry prop min adders signed-digit fast carry prop residue adders adders adders Manchester carry parallel conditional carry carry chain select prefix sum skip T = O(N), A = O(N) T = O(1), A = O(N) T = O(log N) A = O(N log N) T = O(  N), A = O(N) T = O(N) A = O(N)

CSE477 L21 Multiplier Design.4Irwin&Vijay, PSU, 2002 Multiply Operation  Multiplication as repeated additions multiplicand multiplier partial product array double precision product N 2N N can be formed in parallel

CSE477 L21 Multiplier Design.5Irwin&Vijay, PSU, 2002 Shift & Add Multiplication  Right shift and add l Partial product array rows are accumulated from top to bottom on an N-bit adder l After each addition, right shift (by one bit) the accumulated partial product to align it with the next row to add l Time for N bits T serial_mult = O(N T adder ) = O(N 2 ) for a RCA  Making it faster l Use a faster adder l Use higher radix (e.g., base 4) multiplication -Use multiplier recoding to simplify multiple formation l Form partial product array in parallel and add it in parallel  Making it smaller (i.e., slower) l Use an array multiplier -Very regular structure with only short wires to nearest neighbor cells. Thus, very simple and efficient layout in VLSI -Can be easily and efficiently pipelined

CSE477 L21 Multiplier Design.6Irwin&Vijay, PSU, 2002 Tree Multiplier Structure partial product array reduction tree fast carry propagate adder (CPA) P (product) mux + reduction tree (log N) + CPA (log N) Q (‘ier) D (‘icand) D D D multiple forming circuits

CSE477 L21 Multiplier Design.7Irwin&Vijay, PSU, 2002 (4,2) Counter  Built out of two (3,2) counters (just FA’s!) l all of the inputs (4 external plus one internal) have the same weight (i.e., are in the same bit position) l the internal output is carried to the next higher weight position (indicated by the ) (3,2) Note: Two carry outs - one “internal” and one “external”

CSE477 L21 Multiplier Design.8Irwin&Vijay, PSU, 2002 Tiling (4,2) Counters  Reduces columns four high to columns only two high l Tiles with neighboring (4,2) counters l Internal carry in at same “level” (i.e., bit position weight) as the internal carry out (3,2)

CSE477 L21 Multiplier Design.9Irwin&Vijay, PSU, 2002 Tiling (4,2) Counters  Reduces columns four high to columns only two high l Tiles with neighboring (4,2) counters l Internal carry in at same “level” (i.e., bit position weight) as the internal carry out (3,2)

CSE477 L21 Multiplier Design.10Irwin&Vijay, PSU, x4 Partial Product Array Reduction multiplicand multiplier partial product array reduced pp array (to CPA) double precision product  Fast 4x4 multiplication using (4,2) counters

CSE477 L21 Multiplier Design.11Irwin&Vijay, PSU, x4 Partial Product Array Reduction multiplicand multiplier partial product array reduced pp array (to CPA) double precision product  Fast 4x4 multiplication using (4,2) counters

CSE477 L21 Multiplier Design.12Irwin&Vijay, PSU, x8 Partial Product Array Reduction ‘icand ‘ier partial product array How many (4,2) counters minimum are needed to reduce it to 2 rows?

CSE477 L21 Multiplier Design.13Irwin&Vijay, PSU, x8 Partial Product Array Reduction ‘icand ‘ier partial product array reduced partial product array How many (4,2) counters minimum are needed to reduce it to 2 rows? Answer: 24

CSE477 L21 Multiplier Design.14Irwin&Vijay, PSU, 2002 Alternate 8x8 Partial Product Array Reduction ‘icand ‘ier partial product array reduced partial product array More (4,2) counters, so what is the advantage?

CSE477 L21 Multiplier Design.15Irwin&Vijay, PSU, 2002 Array Reduction Layout Approach multiple generators multiplicand multiple selection signals (‘ier)... 2 (4,2) counter slice CPA

CSE477 L21 Multiplier Design.16Irwin&Vijay, PSU, 2002 Next Lecture and Reminders  Next lecture l Shifters, decoders, and multiplexers -Reading assignment – Rabaey, et al,  Reminders l Project final reports due December 5 th l HW5 (last one!) due November 19 th l Final grading negotiations/correction (except for the final exam) must be concluded by December 10 th l Final exam scheduled -Monday, December 16 th from 10:10 to noon in 118 and 121 Thomas