Microelectronics User Group Meeting TWEPP 2015, Lisbon, Portugal 1/10/2015

Agenda “News on foundry access services” by Kostas Kloukinas (CERN) (10’) “Library Characterization Techniques for 65nm and 130nm Technologies.” by Xavi Llopart (CERN) (40’) “TID Effects in 65nm Transistors: Summary of a Long Irradiation Study at the CERN X-rays Facility” by Federico Faccio (CERN) (40’) “Europractice EDA tools for the HEP community: 2015 update” by Emily VAN DER HEIJDEN (STFC) (15’) “Open Discussion” 1/10/15 2

News on foundry access services Kostas Kloukinas TWEPP 2015, Lisbon, Portugal 1/10/2015

Supported Technologies 1/10/15 CMOS 65nm High performance technology for dense designs CMOS 65nm High performance technology for dense designs 65nm CMOS 4 130nm CMOS CMOS 130nm Cost efficient technology for Analog & RF designs CMOS 130nm Cost efficient technology for Analog & RF designs TSMC CMOS 8RF-LM Low cost technology for Large Digital designs CMOS 8RF-LM Low cost technology for Large Digital designs CMOS 8RF-DM Low cost technology for Analog & RF designs CMOS 8RF-DM Low cost technology for Analog & RF designs BiCMOS 8WL-HP High Performance technology for demanding RF designs 130nm CMOS CMOS 6SF Legacy designs CMOS 6SF Legacy designs 250nm CMOS GlobalFoundries  CERN participates on all MOSIS MPW runs (4 runs/year) and organizes ad-hoc MPWs, engineering and production runs TSMC  CERN participates on Cybershuttles and runs via Europractice (IMEC)

Support for IBM technologies Assignment of commercial contract to MOSIS  Contract reassignment procedure completed !  Confidential Disclosure Agreements (CDA) of all institutes passed to GlobalFoundries  Favorable pricing conditions (NRE & production runs)  6 month advance notice of service discontinuity  130nm process has currently very high Turn Around Time (~5 months)  250nm process has low Turn Around Time (~3 months) CERN continues to provide technical support for the 130nm MS Design Kit  Last version is V1.8 Foundry access  Coordination and Purchase orders by CERN  MPWs, Engineering & Production runs via MOSIS Design Tape Out directly to MOSIS Tape Out technical support by MOSIS 25/9/ GF

Support for TSMC technologies CERN & Cadence VCAD does the development and maintenance of the 130nm & 65nm Mixed Signal Design kits Europractice (IMEC) distributes the design kits to our community and provides technical support  Contact IMEC to sign an NDA & request access to the Mixed Signal Kits (IMEC has a list of CERN collaborating  No access fees. Pay-per-use scheme. A 7% fee is applied on the fabrication cost (prototyping, engineering & production runs). This fee covers part of the Mixed Signal Design Kit maintenance costs Projects that make use of the Mixed Signal Design Kit must seek fabrication services exclusively via CERN and IMEC service  Access to foundry services Contact CERN to inform about your submission plans CERN maintains a planning for the year ahead, making an effort to coordinate submissions to share prototyping costs CERN issues common purchase orders to IMEC, receive the fabricated chips and distribute them to designers 1/10/15 6

Support for TSMC technologies Development of the 65 nm Mixed Signal Design Kit  Status: In production. Distribution and technical support by IMEC  Planning: New version in 2016Q1 Development of the 130 nm Mixed Signal Design Kit  Beta 1 version (obsolete) Distribution to CERN designers and small number of outside institutes QRC does not extract RDL parasitics when RDL is used as a routing layer Foundry standard IO pad library at 3.3V  Beta 2 version in production. Distribution and technical support by IMEC QRC with RDL support Adjustments in digital on top implementation flow Integrate 2.5V foundry standard IO pad library  Planning: New version in 2016Q1. Subcontract work to Cadence (VCAD) Digital Back-end implementation flow update 25/9/2015 7

Support for TSMC technologies IP blocks distributed by CERN (contact CERN to obtain access)  65 nm process RadTol (SET tolerant) SRAM compiler (IMEC)  Compiler fully delivered. Silicon prototype tests in progress. efuse IP block from foundry RadTol IO pads (using thin gate devices)  Silicon proven Monitoring ADC  Silicon prototype tests in progress Bandgap reference voltage generator  130 nm process RadTol (SET tolerant) SRAM compiler (IMEC)  Development work in progress. Expect delivery end of 2015 efuse IP block from foundry RadTol IO pads (using thin gate devices)  Outsource the development of the ESD structurs  Work is starting. Expect availability in 2016Q2 Bandgap reference voltage generator 25/9/2015 8

IP block support Call for the community to contribute IP blocks in a common repository Reduce ASIC development effort by sharing and reuse Especially significant for newly introduced processes 1/10/15 9 Effort sharing is important. After all, we all are on the same boat !

Training Workshops A series of Training Workshops will be organized  To present the 65nm Mixed Signal Design Kit  To present Analog and Mixed Signal design Workflows  Cadence (VCAD) design services team: Prepared the training lectures and the accompanying documentation Will provide engineers to lecture in the courses.  3 days training with lectures and hands-on design exercises  Workshop modules based on a realistic Mixed Signal Design  Training material (scripts, design examples and documentation) will be made available to participants  5 training sessions took place at CERN in  Call for interest to organize one more session in 2015Q4 Example Mixed Signal ASIC: “8-bit DAC with I 2 C serial interface” 1/10/15 10

Contacts Contacts at CERN for foundry services  Generic address:  Gert Olesen Coordinates all logistics procedures (administrative, financial, silicon handling) of the foundry services operations  Wojciech Bialas Support for Design kit installations and analog front-end ( Virtuoso ) tools  Kostas Kloukinas General support matters Contacts at IMEC for TSMC support  To request access for the CERN Mixed Signal kits:  For technical support: 1/10/15 11

1/10/15 12

TSMC NDA legal aspects Non Disclosure Agreement (NDA) and Master Technology Usage Agreement (NDA-MTUA)  3-party NDA: TSMC- IMEC – Institute Permitting the distribution of technology information from IMEC to institutes, including layouts of std. cell libraries Permitting institutes to exchange technical data and work in collaboration  Covers both 65nm and 130nm processes  Confidentiality of technical data and documentation Technology data should reside in institutes secure servers and workstations Accessing technology data remotely is not allowed Portable computers storing foundry documentation shall use encrypted storage  Allows for modifications on TSMC technologies (design kit & IP blocks) With TSMC prior agreement At the User’s own risk Title and ownership to any modified TSMC Technologies, including any intellectual property rights in the modifications, remains on TSMC ownership 1/10/15 13

TSMC NDA legal aspects  Unless otherwise agreed by TSMC in writing, the TSMC Technologies are not intended for use in: automotive applications medical applications except for medical imaging systems any military applications nuclear materials related to defense system or power systems aerospace application except fundamental scientific research and dosimetry  Sale of chips is permitted except for banned applications  Export control restrictions Comply with all applicable national export control laws, regulations, and rules Institutes that will receive silicon from CERN must sign and return to CERN a “Letter of Compliance Concerning Deep-Submicron Technology Circuits” All NDAs issued by IMEC are identical. Neither IMEC nor the foundry are willing to negotiate 35+ times with all single Institutes 1/10/15 14

TSMC NDA legal aspects The new NDA will invalidate and supersede all previous NDAs signed between IMEC and Institutes for 65nm &130nm processes prior to entering this new scheme  Old NDAs are very restrictive and are not compatible with the HEP community collaborative work model IMEC will set up and maintain a secure database with the list of Institutes that have signed the new NDA  Institutes that wish to exchange technology information with other institutes must log in and consult this list  IMEC will not accept submission under the CERN contract from Institutes with the “old” NDA in place The responsibility of individual designers in case of breach of confidentiality is required and will be controlled by personalized documents that have to be signed and returned to IMEC 15 1/10/15