University of Toronto Power Grid Verification in the Presence of Uncertainty Farid N. Najm University of Toronto Imad A. Ferzli University.

Slides:



Advertisements
Similar presentations
University of Toronto Minimization of Delay Sensitivity to Process Induced Vth Variations Georges Nabaa Farid N. Najm University of Toronto
Advertisements

Topics Electrical properties of static combinational gates:
Variation Aware Gate Delay Models Dinesh Ganesan.
ELEC 301 Volkan Kursun Design Metrics ECE555 - Volkan Kursun
Efficient Design and Analysis of Robust Power Distribution Meshes Puneet Gupta Blaze DFM Inc. Andrew B. Kahng.
Risk Management and Operations Solutions Derivative Pricing for Risk Calculations – Challenges and Approaches Research Workshop.
On the Need for Statistical Timing Analysis Farid N. Najm University of Toronto
Adaptive Control of a Multi-Bias S-Parameter Measurement System Dr Cornell van Niekerk Microwave Components Group University of Stellebosch South Africa.
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer.
Parameterized Timing Analysis with General Delay Models and Arbitrary Variation Sources Khaled R. Heloue and Farid N. Najm University of Toronto {khaled,
Minimal Skew Clock Synthesis Considering Time-Variant Temperature Gradient Hao Yu, Yu Hu, Chun-Chen Liu and Lei He EE Department, UCLA Presented by Yu.
Path Finding for 3D Power Distribution Networks A. B. Kahng and C. K. Cheng UC San Diego Feb 18, 2011.
CS 589 Information Risk Management 23 January 2007.
1 A Variation-tolerant Sub- threshold Design Approach Nikhil Jayakumar Sunil P. Khatri. Texas A&M University, College Station, TX.
Device Sizing Techniques for High Yield Minimum-Energy Subthreshold Circuits Dan Holcomb and Mervin John University of California, Berkeley EE241 Spring.
TH EDA NTHU-CS VLSI/CAD LAB 1 Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University.
Institute of Digital and Computer Systems 1 Fabio Garzia / Finding Peak Performance in a Process23/06/2015 Chapter 5 Finding Peak Performance in a Process.
PED Roadmapping Issues Vijaykrishnan Narayanan Dept. of CSE Penn State University GSRC Workshop, March 20-21, 2003.
Alpha Goal: very fast multiprocessor systems, highly scalable Main trick is high-bandwidth, low-latency data access. How to do it, how to do it?
1 Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization TingTing Hwang Tsing Hua University, Hsin-Chu.
Economics. Contd. Economics is essentially the study of logic, tools and techniques of making optimum use of the available resources to achieve given.
The CMOS Inverter Slides adapted from:
More Realistic Power Grid Verification Based on Hierarchical Current and Power constraints 2 Chung-Kuan Cheng, 2 Peng Du, 2 Andrew B. Kahng, 1 Grantham.
1 D r a f t Life Cycle Assessment A product-oriented method for sustainability analysis UNEP LCA Training Kit Module k – Uncertainty in LCA.
Logic Optimization Mohammad Sharifkhani. Reading Textbook II, Chapters 5 and 6 (parts related to power and speed.) Following Papers: –Nose, Sakurai, 2000.
11 1 Process Variation in Near-threshold Wide SIMD Architectures Sangwon Seo 1, Ronald G. Dreslinski 1, Mark Woh 1, Yongjun Park 1, Chaitali Chakrabarti.
Steve Grout CAD Consultant April 26, 2004 Missing Analog Tools – A Proposal Analog/Mixed Signal SoC Methodologies.
Materials Process Design and Control Laboratory THE STEFAN PROBLEM: A STOCHASTIC ANALYSIS USING THE EXTENDED FINITE ELEMENT METHOD Baskar Ganapathysubramanian,
CRESCENDO Full virtuality in design and product development within the extended enterprise Naples, 28 Nov
Probabilistic Mechanism Analysis. Outline Uncertainty in mechanisms Why consider uncertainty Basics of uncertainty Probabilistic mechanism analysis Examples.
1 Chapter 8: Procedure of Time-Domain Harmonics Modeling and Simulation Contributors: C. J. Hatziadoniu, W. Xu, and G. W. Chang Organized by Task Force.
On-chip power distribution in deep submicron technologies
Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics;
Statistical Sampling-Based Parametric Analysis of Power Grids Dr. Peng Li Presented by Xueqian Zhao EE5970 Seminar.
Tarek A. El-Moselhy and Luca Daniel
Robust Low Power VLSI ECE 7502 S2015 Minimum Supply Voltage and Very- Low-Voltage Testing ECE 7502 Class Discussion Elena Weinberg Thursday, April 16,
An ATD Model that Incorporates Uncertainty R. Ian Sykes Titan Research & Technology Div., Titan Corp. 50 Washington Road Princeton NJ OFCM Panel Session.
STA with Variation 1. 2 Corner Analysis PRCA (Process Corner Analysis):  Takes 1.nominal values of process parameters 2.and a delta for each parameter.
General ideas to communicate Dynamic model Noise Propagation of uncertainty Covariance matrices Correlations and dependencs.
Optimal Placement of Energy Storage in Power Networks Christos Thrampoulidis Subhonmesh Bose and Babak Hassibi Joint work with 52 nd IEEE CDC December.
IBM Microelectronics © 2005 IBM Corporation SLIP 2005April 2, 2005 Bounding the Impact of Transient Power Supply Noise in Static Timing Analysis Over a.
Xuanxing Xiong and Jia Wang Electrical and Computer Engineering Illinois Institute of Technology Chicago, Illinois, United States November, 2011 Vectorless.
Power Integrity Test and Verification CK Cheng UC San Diego 1.
Monte-Carlo based Expertise A powerful Tool for System Evaluation & Optimization  Introduction  Features  System Performance.
EE 201C Modeling of VLSI Circuits and Systems
EE201C : Stochastic Modeling of FinFET LER and Circuits Optimization based on Stochastic Modeling Shaodi Wang
Summary of FPIX tests Tom Zimmerman Fermilab May 16, 2007.
Uncertainties in fluid-structure interaction simulations
Company Confidential | ©2009 Micron Technology, Inc. | 1 Micron Contact: Tim Hollis February 16 University of Utah Senior.
EE415 VLSI Design THE INVERTER [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Uncertainty and Reliability Analysis D Nagesh Kumar, IISc Water Resources Planning and Management: M6L2 Stochastic Optimization.
Forward and Backward Deviation Measures and Robust Optimization Peng Sun (Duke) with Xin Chen (UIUC) and Melvyn Sim (NUS)
1 Chapter 5 Branch-and-bound Framework and Its Applications.
Geraint Palmer Optimisation using Linear Programming.
Proximity Optimization for Adaptive Circuit Design Ang Lu, Hao He, and Jiang Hu.
Probabilistic Slope Stability Analysis with the
1 Life Cycle Assessment A product-oriented method for sustainability analysis UNEP LCA Training Kit Module k – Uncertainty in LCA.
Unified Adaptivity Optimization of Clock and Logic Signals Shiyan Hu and Jiang Hu Dept of Electrical and Computer Engineering Texas A&M University.
MICROPROCESSOR DESIGN1 IR/Inductive Drop Introduction One component of every chip is the network of wires used to distribute power from the input power.
ENGINEERING MANAGEMENT – MEM
Nodal Methods for Core Neutron Diffusion Calculations
VLSI Design MOSFET Scaling and CMOS Latch Up
Challenges in Nanoelectronics: Process Variability
Chapter 5a On-Chip Power Integrity
Circuit Design Techniques for Low Power DSPs
EE 201C Modeling of VLSI Circuits and Systems
Post-Silicon Calibration for Large-Volume Products
Combinational Circuit Design
Hardware Implementation of Simplex Algorithm for Flash ADC Optimization Yuta Toriyama April 09, 2010.
Presentation transcript:

University of Toronto Power Grid Verification in the Presence of Uncertainty Farid N. Najm University of Toronto Imad A. Ferzli University of Toronto

Ferzli/NajmECE Graduate Symposium2 Uncertainty: A Critical Constraint n The crux of the problem: key decisions for the power grid need to be made even before design/layout l How does one design robust grids that meet IR drop budgets? n The backbone: a solid “grid verifier” that incorporates uncertainty in the design…and the process! n Uncertainty, ascertained: l Switching currents: not known pre-placement l Leakage currents: very sensitive to on-chip process variations l Grid parasitics

Ferzli/NajmECE Graduate Symposium3 Grid Verification Methodology

Ferzli/NajmECE Graduate Symposium4 Switching Currents n Incremental constraint-based approach (work done with Dionysios Kouroussis) l Preserves vectorless, conservative characteristics of constraint- driven power grid verification l Combines a “divide-and-conquer” approach with “local” grid properties l Is to power grid analysis what static timing is to timing analysis n DC analysis done, transient analysis in progress

Ferzli/NajmECE Graduate Symposium5 Leakage Currents n Power grid verification formulated as a probability that IR drop on one or several nodes exceeds a certain threshold l Analysis involves statistical and numerical Monte Carlo techniques V Iswitching V Ileak,nom V Ileak,dd V Ileak,wd Nominal supply voltage (Vdd) Allowable voltage level (e.g. 90%Vdd)

Ferzli/NajmECE Graduate Symposium6 Grid Parasitics n Higher chip currents, tighter noise margins make parasitic (R, L, C) variations an important concern n Complicated problem: l Size of the system to be solved l Statistical correlations l No trivial worst case n Framework: l Decorrelation of physical variations l Expansion of grid voltages in terms of orthogonal polynomials (“polynomial chaos”) l Solution of a stochastic system