Fast VLSI Implementation of Sorting Algorithm for Standard Median Filters Hyeong-Seok Yu SungKyunKwan Univ. Dept. of ECE, Vada Lab. Paper : FP 1.3

VLSI Algorithmic Design Automation Lab ASIC Conference 2  Introduction Signal and image processing applications Smooth the Noisy signals & Preserving the edge information Smoothing Techniques Linear Filtering Median Filtering

VLSI Algorithmic Design Automation Lab ASIC Conference 3  Introduction (cont') Design Method ( H/W vs. F/W & S/W )

VLSI Algorithmic Design Automation Lab ASIC Conference 4  Median Filtering 1-D Median Input signals : x 1, x 2, x 3,..., x (s-1), x (s) Window sizes : w = 2k + 1 Median Output yi = Median [x (i-k),..., x (i-1), x i, x (i+1),..., x (i+k) ]

VLSI Algorithmic Design Automation Lab ASIC Conference 5  The Algorithm Median Filter for General-purpose signal or Image processor different word lengths extensible window sizes real time rate Target algorithm for VLSI implementation Only a few simple units A simple and regular communication & control scheme simple window size extension & no time delay increase no feedback loop for the availability of pipelining

VLSI Algorithmic Design Automation Lab ASIC Conference 6  The Algorithm (cont’) The conventional single array structures Reference [5], [7], [8], [10], [11], [12], [13] Disadvantages A feedback loop - pipelining, delay, complexity non-linear delay-increase for extracting the rank order Excessive memory elements

VLSI Algorithmic Design Automation Lab ASIC Conference 7  The Algorithm (cont') The single array insertion sorting of the ordered list using History Matrix Reducing area Less switching activity Higher throughput Efficient VLSI implementation

VLSI Algorithmic Design Automation Lab ASIC Conference 8  The Algorithm (cont') A filter array for proposed algorithm Cascade of cells Simple inter-communication with adjacent cells

VLSI Algorithmic Design Automation Lab ASIC Conference 9  The Algorithm (cont') Definition of symbols z : i-th ordered cell values h : i-th row elements d : a lower cell u : an upper cell p : a present cell h(i, j) : elements from i-th to j-th column History Matrix The set of the elements with 0 or 1 The w  w number of 1 bit flip-flop

VLSI Algorithmic Design Automation Lab ASIC Conference 10  The Algorithm (cont') The operation of History Matrix i-th column : rank ( # of ‘1’ ) of i-th input data reversely The elements of row of first column  New input data  1 predictive < New input data  0 The elements of other rows up transition of unit value : replace with lower rows down transition of unit value : replace with upper rows no transition of unit value : replace or shift It contains index values and rank values

VLSI Algorithmic Design Automation Lab ASIC Conference 11  The Algorithm (cont') Processing sequence of unit values and matrix Initially, all the elements of the matrix = 1 and filled by 0 Sorted in decreasing order x | y : the unit value index | the unit value

VLSI Algorithmic Design Automation Lab ASIC Conference 12  The Algorithm (cont') The extracting operation of rank of each cell example of window size 5 x 5

VLSI Algorithmic Design Automation Lab ASIC Conference 13  The Algorithm (cont') Proposed filter cell architecture simple control : a few gates, mux, shift reg. memory unit : unit value and a single row of History Matrix

VLSI Algorithmic Design Automation Lab ASIC Conference 14  Conclusions Experimental Results 25 ns delay reported by SYNOPSYS TM 40 MHz clock frequency for 8 bit word-length bps operation always same delay for different window size 1185 gates for window size= 5 Summarized comparison results