(Re)design of the C3PD analog pixel 1

The starting point for the design was the CCPDv3 front-end (this presentation tries to follow the way the design was done) Simulations shown in this presentation are done at a schematic level (the design is particularly sensitive to parasitic capacitances) (extraction required to validate numbers) The comparisons were done schematic to schematic with 20fF load 2 Notes

nwell p+ dnwell psub p+ Substrate (-40V) p+ Any p+/nwell diffusion is potentially a path to inject noise into the detector Ground (0V) nwell (~1.75V)

VBiasPreamp VPLoad BLR Vout nwell C COUPL VCasc Vin 40fF BL 12fF Gate 14uA NWELL biasing not shown 5 PMOS transistors (+2 for sensor biasing) 2 stages (1 st capacitively loaded) CSA (Cout penalises BW) Low gain stage (3 at peak, open loop) 14.3uA total current consumption 2 power supplies (PMOS input) Test pulse injection common to all pixels 300nA

Vcasc VBiasPreamp VBiasPreampCasc VBiasLS VBiasFBK Vout TPEn_Rown TPInject C TEST nwell C COUPL NWELL biasing not shown 1.5 PMOS transistors (+2 for sensor biasing) 2 stage (in a closed loop!) Amplifier Unity gain buffer 2.5uA total current consumption 1 power supply (NMOS input) Test pulse injection selectable to individual pixels 2uA 500n Biasing generated in the periphery For the simulations in the coming slides a 20fF capacitance was added at the output for the two systems

Vcasc VBiasPreamp VBiasPreampCasc VBiasLS VBiasFBK Vout TPEn_Rown TPInject C TEST nwell C COUPL NWELL biasing not shown 1.5 PMOS transistors (+2 for sensor biasing) 2 stage (in a closed loop!) Amplifier Unity gain buffer 2.5uA total current consumption 1 power supply (NMOS input) Test pulse injection selectable to individual pixels 2uA 500n Biasing generated in the periphery For the simulations in the coming slides a 20fF capacitance was added at the output for the two systems Metal to metal

7 Original amplifier Redesigned circuit Original amplifier Redesigned circuit Response to a delta dirac pulse at the input (1000e - injected) Response to simulated pulse (injected at the center of the pixel)

8 Original amplifier Redesigned circuit Original amplifier Redesigned circuit Response to a delta dirac pulse at the input (1000e - injected) Response to simulated pulse (injected at the center of the pixel)

Response to a delta dirac pulse at the input (for different input charges) Feedback capacitance 0.33fF (parasitic d-s)

10 Soon first checks with the extracted view…

11 Original Design NWELL biasing not shown 5 PMOS transistors (+2 for sensor biasing) 2 stages (1 st capacitively loaded) CSA (Cout penalises BW) Low gain stage (3 at peak, open loop) 14.3uA total current consumption 2 power supplies (PMOS input) Test pulse injection common to all pixels Proposed version NWELL biasing not shown 1.5 PMOS transistors (+2 for sensor biasing) 2 stage (in a closed loop!) Amplifier Unity gain buffer 2.5uA total current consumption 1 power supply (NMOS input) Test pulse injection selectable to individual pixels

cf rf +1 gmvxgmvx ro co vivi vovo idid cd Small signal model 12 cl Matlab file: c:\rafa_documents\WORK\VELOPIX\Preamplifier\AnalysisPreamplifierWithWithoutBuffer.m Mathematica file: C:\rafa_documents\WORK\FrontEndParameters\CSAequationsWithBufferHVCMOS.nb ccoupl We apply the dominant pole approximation GBW Feedback vxvx