IEEE Bipolar/BiCMOS Circuits and Technology Meeting Zach Griffith, Mattias Dahlström, and Mark J.W. Rodwell Department of Electrical and Computer Engineering University of California, Santa Barbara, CA, USA Miguel Urteaga, Richard Pierson, Petra Rowell, and Bobby Brar Rockwell Scientific Corporation, Thousand Oaks, CA, USA Sangmin Lee, Nguyen Nguyen, and Chanh Nguyen Global Communication Semiconductors, Torrance, CA, USA , fax Ultra High Frequency Static Dividers > 150 GHz in a Narrow Mesa InGaAs/InP DHBT Technology

ParameterInP/InGaAsSi/SiGebenefit (simplified) collector electron velocity3E7 cm/s1E7 cm/slower  c, higher J base electron diffusivity40 cm 2 /s~2-4 cm 2 /slower  b base sheet resistivity 500 Ohm5000 Ohmlower R bb comparable breakdown fields Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation ~3:1 higher breakdown at a given bandwidth Problems for InP HBTs: SiGe has much better scaling & parasitic reduction Present efforts in InP HBT research community Development of low-parasitic, highly-scaled, high-yield fabrication processes Why mesa DHBT? Simple way to continue the advance of epitaxial material for improved speed Motivation for InP HBTs

High speed HBT: some standard figures of merit Small signal current gain cut-off frequency (from H 21 )… Power gain cut-off frequency (from U)… Collector capacitance charging time when switching…

MS flip-flops are very widely-used high speed digital circuits: Master-Slave Flip-Flop with inverting feedback Connection as 2:1 frequency divider provides simple test method Standard benchmark of logic speed: Performance comparisons across technologies Dynamic, super-dynamic, frequency dividers: Higher maximum frequency than true static dividers Narrow-band operation  applications are limited High Speed technology performance: UCSB / RSC / GCS: 152 GHz static divider using InGaAs/InP mesa DHBT IBM: 96 GHz static divider using advanced mesa Si/SiGe HBT Why Static Frequency Dividers ? A. Rylyakov, T. Zwick, IEEE GaAsIC Symposium, 2003

Divide-by-2 versus Divide-by-4 Divide-by-2 latch with feedback 300 mV pp buffer, 50 Ohm loading easily tested with sampling scope or spectrum analyzer Divide-by-4 2 stages interstage buffer has 25 Ohm loading easily tested with sampling scope or spectrum analyzer

How do we make HBTs faster… key device parameter required changes to double bandwidth collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 0.707:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter resistance per unit emitter areadecrease 4:1 current densityincrease 4:1 base contact resistivity (if contacts lie above collector junction) decrease 4:1 base contact resistivity (if contacts do not lie above collector junction) unchanged What we improved at the device level to increase this generation of ckt speed (C ’s,  ’s, C/I ’s all reduced 2:1) …easily derived from geometry / resistivity / velocity relationships Reduced from 200 nm to 150 nm Reduced from 0.7  m to 0.5  m Reduced from 30 to 20  m 2 Increased by factor 2.5

InGaAs 3E19 Si 40 nm InP 3E19 Si 80 nm InP 8E17 Si 10 nm InP 3E17 Si 30 nm InGaAs 8E19  5E19 C 30 nm Setback 3E16 Si 20 nm InP 3E18 Si 3 nm InP 3E16 Si 103 nm SI-InP substrate Grade 3E16 Si 24 nm InP 1.5E19 Si 50 nm InGaAs 2E19 Si 12.5 nm InP 3E19 Si 300 nm Compared to previous UCSB mesa HBT results: Thinner InP collector—decrease  c Collector doping increased—increase J Kirk Thinner InGaAs in subcollector—remove heat Thicker InP subcollector—decrease R c,sheet DHBT Layer Structure for high f  and digital ckts V be = 0.75 V, V ce = 1.3 V Emitter Collector Base

Mesa DHBTs with 150 nm collector 0.6 x 7  m 2 emitter junction 15  -  m 2 contact resistivity 30 nm InGaAs base 8  /cm 3 →5  /cm 3 grade 603  /square 0.5  m wide base contacts 20  -  m 2 contact resistivity 150 nm collector 20 nm InGaAs setback layer 24 nm InGaAlAs superlattice grade 103 nm InP remaining thickness 0.2  m collector undercut

RF performance—record f , high f max, and low C cb /I c Griffith et al, IEEE Electron Device Letters—May 2004

Device modeling of transistor Details of device parasitics Withdrawn from device, added externally C cb calculated from particular device dimensions  cont and  sheet measured from TLMs  collector  3.5  10 7 cm/sec, V turn-on = 0.9 V

Fast divider design—design considerations

Why isn't base+collector transit time so important for logic? Depletion capacitances present over full voltage swing, no large-signal reduction

Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse Collector capacitance charging time scales linearly with collector thickness if J = J max Fast divider design—device considerations

  ex  7  m 2 needed for 200 GHz clock rate ECL delay not well correlated with f  or f max Key HBT Scaling Limit  Emitter Resistance Largest delay is charging C cb  J e  10 mA/  m 2 needed for 200 GHz clock rate Voltage drop of emitter resistance becomes excessive R ex I c =  ex J e = (15  m 2 )  (10 mA/  m 2 ) = 150 mV  considerable fraction of  V logic  300 mV Degrades logic noise margin

+V 0V kzkz Microstrip modeSubstrate modes +V 0V CPW mode 0V CPW has parasitic modes, coupling from poor ground plane integrity kzkz Microstrip wiring has… -V0V+V 0V Slot mode -- ground straps suppress slot mode, …but multiple ground breaks in compex ICs produce ground return inductance -- ground vias suppress microstrip mode, wafer thinning suppresses substrate modes Trade-offs between interconnect wiring environments high via inductancehas mode coupling unless substrate is thin

Thin-film microstrip wiring, inverted is best for complex ICs Divider before ground plane deposition Divider after ground plane deposition

Design approach for fast logic Objective… Design a divider to operate at  150 GHz UCSB’s approach—how to get to 150 GHz… Employ single level ECL for the data and clk level on both the acquire and hold sections of divider Microstrip wiring environment with low loss  r = 2.7 Minimize (  V logic C cb /I c ) loading: Use small devices operating at high current density Add small peaking inductance to data bus to shorten data transition time Simulated results with distributed device model… Maximum frequency divider speed  168 GHz

UCSB DHBTs withstand ECL voltages when biased at the currents needed for speed

Layout and simulated performance 582  m 533  m Simulated divider speed w/ TFAST device model… T c = 150 nm, T b = 40 nm R ex,cont  30  m 2, R bb, cont  20  m 2 Resistive pulldown only R Load = 45 , f max = 122 GHz R Load = 35 , f max = 129 GHz R Load = 25 , f max = 133 GHz w/ Inductive peaking = 62 pH R Load = 45 , f max = 136 GHz R Load = 35 , f max = 150 GHz R Load = 25 , f max = 168 GHz

Precise Details of 150 GHz UCSB/RSC/GCS divider units data current steering data emitter followers clock current steering clock emitter followers size m2m2 0.5 x 40.5 x x 6 current density mA/  m C cb /I c ps / V V cb V ff GHz f max GHz Key features in the divider design: Circuit topology—emitter coupled logic (ECL) inductive peaking ~ 62 pH no clock input buffer used—single ended clk drive power dissipation, divider core only = mW power dissipation, w/ output buffer = mW devices sized to either operate at… J Kirk for minimum C cb /I c ratio sizes large enough where I E  R ex potential drops are not a significant portion of  V logic

Low frequency clocking and sensitivity of 150 GHz divider Output 1.5 GHz, f clk = 3 GHzVariation of input sensitivity with frequency The divider is operational from 152 GHz down to 3 GHz at identical DC bias conditions this confirms the circuit is fully static The sensitivity plot shows a divider self-oscillation frequency of ~ 87 GHz

UCSB/RSC/GCS static divide-by-2 circuit at 152 GHz Span DC to 77 GHzSpan 5 MHz Measurements performed at Mayo with RSC and UCSB Participation RSC Wafer #GCS12-005, Divider ID: R3C4 #48, Fabricated at GCS, Design at UCSB VDI Source Used For CLK Input, V clk offset  -1.7 V, V EE = V, I EE = 162.1mA, P DC,total = mW Power dissipation of divider core without output buffer  mW—tested at room temp (25  C)

UCSB/RSC/GCS static divide-by-4 circuit at 137 GHz Span DC to 50 GHzSpan 100 MHz Measurements performed at UCSB, GUNN Source Used For CLK Input RSC Wafer #GCS12-005, Divider ID: R3C4 #48, Fabricated at GCS, Design at UCSB V clk offset  -1.7 V, V EE, div2 = V, I EE, div2 = mA, V EE, div4 = V, I EE, div4 = mA Power dissipation of divider core without output buffer  mW—tested at room temp (25  C)

142 GHz divide by 2--fabricated at UCSB Nanofab Bias conditions: P total = mW P core  800 mW I ee = 210 mA V ee = V f clk,min = 3 GHz Span DC to 75 GHzSpan 5 MHz

UCSB/RSC/GCS static divide-by-2 circuit temp comparison Wafer chuck 25  CWafer chuck 20  C Dividers are not being minimum gate delay limited —they are being thermally limited by the input clock devices Because of device operating conditions for the clock input devices (V ce  2.6 V, J e  5 mA/  m 2, P  13 mW/  m 2 ), they get hot Moderate cooling needed in order to improve/increase circuit performance RSC Wafer #GCS12-005, Divider ID: R3C4 #48 f clk = 150 GHz, Pout = dBmf clk = 152 GHz, Pout = dBmf clk = 153 GHz, Pout = dBm

Conclusion Static frequency dividers measured to a high f clk = 152 GHz Circuit performance increased by doing the following: – Emitter coupled logic (ECL) topology and peaking inductance – Reduced collector thickness, 150 nm – Device operation at J Kirk for respective V cb – Reduced base-collector mesa area, A c / A e  3.0 – Microstrip wiring environment for well behaved impedance at > 100 GHz Continued reduction of device parasitics needed for improved speed – Collector needs to be thinned because C cb  V Logic / I c  T J e = J Kirk – But R ex consumes portions of logic swing as I e  R ex  J e  e  T c -2 Collector pedestal needed for improved speed and reduced power – Reduced C cb / I c for improved speed, Constant C cb / I c for reduced power

Conclusion Thank you Acknowledgements: This work was supported under by DARPA under the TFAST program—N C-8080