Ready to Use Programmable Logic Design Solutions

Foundation Series Xilinx’ Ready-to-Use solution  World-class EDA Technology, Integrated Into a Unified Design Environment  Value-driven Configurations Which Meet Your Design Methodology and Density Needs.  High-volume, Full Featured Programmable Logic Devices.  World Class Field and Factory Support.

Foundation Series Xilinx’ Ready-to-Use solution  World-class EDA Technology, Integrated Into a Unified Design Environment Mixed-level Design Push-Button Flows Superior HDL Solution

World-Class EDA Technology Synopsys Synthesis Xilinx Implementation tools (including A.K.A. Speed Technology) Aldec Design Entry tools Optional RTL Simulation * * VHDL and Verilog Simulation tools from Aldec and MTI sold separately. Ask for details Aldec Gate- Level Simulator K-Paths Enhanced Static Timing Analyzer

Unified Design Environment Design File Management Window with File, and Version tabs Standard Windows Tool Bar Foundation Flow Engine Window with Content, and Report tab Standard Windows Pull-down Menus Flow Button Status Indicator Console Window with Error, Warning, and Messages tabs

Push-Button, Programmable Logic Design Solution  Supporting Your Design Methodology Mixed-level Design Mixed-language Design  Robust and Versatile Analysis Gate-level Simulation HDL Simulation Static Timing Analysis  Xilinx Implementation Tools Great Results by Default Performance Driven When You Need It Design Entry Simulation Synthesis Implementation Foundation Series

Push-Button Performance “Pull automation” identifies dependencies and runs both synthesis and implementation tools Versatile check- point verification capabilities accelerate design process. Enter your design using your preferred method of either schematic, hdl, or state machine FPGA Express TM world class synthesis for all designs which include HDL Device programming at the push of a button Xilinx’ Implementation tools quickly deliver high QOR through Xilinx A.K.A. Speed Technology Optional RTL HDL Source-code debugging

Push-Button Synthesis X X Foundation “Pull Automation” runs both Synthesis and Implementation tools after the push of a single button and completion of the synthesis / implementation dialog. HDL constraint entry / and Time Tracker TM GUIs* illustrate estimates of your design’s critical paths using an intuitive spreadsheet format. * Note - Available in Express configuration only or

Tabs for Global, Port and Advanced Constraints Global (Clock) Constraint Definition User Constraints File display * The Xilinx Constraints Editor is used in Foundation Series Base, Base-Express and Standard product configurations. Push-Button Constraint Entry Xilinx Constraints Editor Global Dialog*

Push-Button Constraint Entry Xilinx Constraints Editor Ports Dialog Port Name and Direction listed by XCE for designer Valid list of I/O locations, Timing Constraints and Slew Rate options listed by XCE for designer

Your Design Methodology Mixed-Level Design Design Wizard automates the process of adding an HDL Symbol into a Schematic HDL Design becomes as easy as schematic entry with drop in blocks of HDL. HDL Editor directly associated with new schematic object

Your Design Methodology Mixed Language Design  Seamless Integration of VHDL and Verilog Supported in Both Synthesis and Simulation  Enables High-density Design Flows to Utilize IP / Cores  Enables High-volume Design Flows to Reuse Designs in Order to Meet Short Time-to-market Demands of Standards Based Design  Xilinx CORE Generator (included) Xilinx designed and delivered, cost effective solutions (i.e. PCI) Alliance-Core Program delivers a wide variety of 3rd party cores.

Robust and Versatile Verification Gate-Level Simulation  Gate-level Simulation Supports Designs Densities Beyond 50 K Gates Cross-highlighting Supports for Schematic Flows Support for Simulation of Gate-level Netlist From Synthesized HDL Provides Both Graphical and Command File Stimulus Capabilities  Simulation Script Wizard and Integrated Editor Simplify Command File Generation

Robust and Versatile Verification HDL Simulation  Enables RTL Source Code Debugging  Supports Test-bench Methodologies  Enables Back-Annotated Timing Simulation using HDL  Supports Push-Button Integration into Foundation PCM Active-VHDL only

Robust and Versatile Verification Static Timing Analysis  Front End Performance Estimates (FPGA Express Time Tracker TM GUI  Detailed Physical Path Timing Analysis (Post-layout) Accelerates Qualification of Design Layout After Functional Verification Available Through an Interactive GUI or in a Variety of Text Report Files.  Evaluates QOR Based on Design Requirements Specified by User.  Supports Min Delays and Timing Pro-rating for Improved Operating Conditions

Xilinx Best-in-Class Implementation Tools  Seamlessly Integrated Into the Foundation Project Manager  Xilinx Flow Engine Simplifies Access to Xilinx A.K.A. Speed Technology  Enables Great Results Automatically  Performance Driven Capabilities When Needed

Superior HDL Solution: Design Creation Graphical State Editor Language Assistant  VHDL & Verilog HDL Design Capabilities Including: Graphical State Diagram Editor Powerful HDL Editor With Integrated Language Assistant Logiblox and CORE Generator Instantiations  VHDL Language Tutorial From Esperan.

Superior HDL Solution: Synthesis  Mixed VHDL & Verilog HDL Synthesis and Optimization  Robust FPGA Express Compiler Includes Support for VHDL ‘93  Time Trackertm Performance Estimator Graphical Constraint Entry / Analysis

Superior HDL Solution: Simulation  Support for VHDL And/or Verilog HDL RTL Source Code Debugging  Supports Testbench Methodologies  Fully Qualified Design Flows  30 Day Evaluation Products Included With Each Foundation Series HDL Product Shipped  Licensing and Support Provided by Simulator Vendors. Permanent licenses sold separately by partners. Visit and for info. on current product offerings.

Xilinx Foundation Series HDL Solutions Productivity Edge Design Wizards Graphical VHDL and Verilog Entry Synopsys Synthesis Performance Driven Design (A.K.A. Speed technology) Best Programmable Logic Performance/Density/Power VHDL / Verilog Simulation (Free Evaluation software in the box) Mixed-Level, Mixed-Language Design Best Timing Driven Compile Time 4 Only Xilinx Delivers These Essential Capabilities

Foundation Series Xilinx’ Ready-to-Use solution  World-Class EDA Technology, integrated into a Unified Design Environment  Value-driven configurations which meet your design methodology and density needs.  High-Volume, full featured Programmable Logic Devices.  World Class Field and Factory Support.

Xilinx Foundation Series Value-Driven configurations NOTE: Promotional Pricing Good Through 12/30/98 $95 $495 $4995! $4995! $3995 $7995 X

Foundation Series Xilinx’ Ready-to-Use solution  World-class EDA Technology, Integrated Into a Unified Design Environment  Value-driven Configurations Which Meet Your Design Methodology and Density Needs.  High-volume, Full Featured Programmable Logic Devices.  World Class Field and Factory Support.

Complete High Volume Solution  Spartan / Spartan XL Fpgas No Compromises Architecture Performance, RAM, Cores, and Low Price  XC9500 / 9500XL Cplds Most Flexible JTAG ISP Devices Fastest Speed, Best Pin-locking, and Low Price

Foundation Series Xilinx’ Ready-to-Use solution  World-class EDA Technology, Integrated Into a Unified Design Environment  Value-driven Configurations Which Meet Your Design Methodology and Density Needs.  High-volume, Full Featured Programmable Logic Devices.  World Class Field and Factory Support.

Foundation Series World Class Support  Expert Field Applications Engineers  Certified Distribution Field Applications Engineers  Rapid-response Xilinx Hot-line Support  “Known-issues” and Solutions Database Available From On-line Documentation and From the Xilinx Support Web Site.  Comprehensive Customer Education Program: Hard Copy Manuals, Including Tutorials On-line Documentation / Reference Manuals On-line Help With Comprehensive Index Local and Factory Based Customer Training Courses