Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions Vishal Suthar and Shantanu Dutt Electrical and Computer Engineering University of Illinois at Chicago.

Outline The problem of fault-free assumptions & other stories Iterative Bootstrapping (IB) – A general solution Mixed BIST: Combining PLB & interconnect testing with IB—no fault-free assumptions –Recent work in PLB BIST (HD-BIST) –Recent work in interconnect BIST (I-BIST) Simulation Results Conclusions

Built-In Self-Test in FPGAs—Basic Concepts TPG - Test Pattern Generator ORA - Output Response Analyser CUT - Cells Under Test Comparison based BIST: WUT - Wires Under Test WUT In each session diff. PLBs act as CUTs, TPG and ORA. TPG CUT ORA Pass / fail WUT Gross syndrome (GS): The gross syndrome of a session is the overall fail/pass (X/√ ) result of a session. Match in all CUT outputs => ORA output = 0 => GS = pass (√ ) Else ORA output = 1 => GS = fail (X)

(V. Verma, S. Dutt, V. Suthar, DAC 2004)BISTer-1: ORA CUT TPG CUT ORA TPG ORA CUT A B C D A A B B C C D D TPG CUT ORA A D B C (S1)(S2)(S3)(S4) Theorem: BISTer-1 is 1/4 diagnosable (1)16.9 (2)26.6 (3) Fault density (cluster density) (%) Fault coverage (%) BISTer-1BISTer-0 (a) Random faults(b) Clustered faults Drawbacks in deterministic BIST techniques

Fallacy of Fault-Free Assumptions 1.Limited / Incorrect diagnosability in presence of multiple faults in the BISTer area. Unrealistic assumptions: a) The test circuit (TPG & ORA) is fault-free. b) No fault masking; c) no more than 1-2 faults in BISTer area TPG CUT ORA GS= pass (non-det.) BISTer 2. Absence of BIST techniques that can diagnose faults present in PLBs as well as interconnects. Unrealistic assumption: while testing PLBs the interconnects used in the BISTer area are fault-free and similarly, while testing interconnects the PLBs forming the test circuit are fault-free. GS= fail (false +ve)

Iterative Bootstrapping (IB) Test circuit with f-free prob. = Use redundancy (e.g. TMR) to increase Test PLBs conf. for ORA and TPG functions & reqd. interconnects using o/p = Test circuit with f-free prob. Test circuit No Yes Final test circuit Need: An ability to detect and diagnose faults in presence of multiple faults and/or clustered fault patterns in both PLBs and interconnects, with high probability. Solution: Iterative bootstrapping for obtaining fault-free test circuits (w/ fault-free PLBs & interconnects)

Iterative Bootstrapping (IB) Does it always work? If not, are there conditions under which it works? Are these conditions realistic? Consider TMR as the redundant circuit: p = prob. of a faulty PLB, q 1 (q 2 ) = prob of fault-free TMR TPG/ORA (1 PLB impl.) in 1 st (2 nd ) iter of IB Theorem: If prob. of correct oper. f(q) [q=fault-free prob. of component] is monotonically non-decreasing, and f(q 0 =1-p) >= 1-p, then IB provides us w/ s sequence of redundant test circuits with monotonically non- decreasing fault-free probabilities q 1, q 2, ….., q k. No Yes

Mixed PLB and Interconnect BIST Two high-diagnosability BIST techniques used. 1.HD-BIST (High-Diagnosability BIST) – PLB testing [GLSVLSI’05] 2.I-BIST (Interconnect BIST) – Interconnect testing [DATE’06] Reqmt for reliable mixed testing w/ faults in PLBs & interconnects: PLB testing Interconnect testing F-free interconnect F-free TPGs/ORAs requires obtained from A classic chicken-&-egg problem (which comes first). Solution: Break the cycle via Iterative Bootstrapping

Mixed PLB and Interconnect BIST (contd) Solution: Break the cycle via IB and then interleave the various stages of HD-BIST and I-BIST so that fault-free components (w/ high prob.) are available to test the next stage. Our approach: First phase – IB w/ TMR Phase test ckt. rqd. for phase Non TMR’ed Fault state unknown

Mixed-BIST: PLB BIST Stages TPG shuffling scheme (instead of TMR) to reduce test vector skipping probability Bootstrapping phases (2) o/p = faulty PLBs Global testing – Fault detection & gross diagnosis phase Detailed testing: Adaptive diagnosis phase o/p = suspect PLBs & fault-free sticks o/p = fault-free ORA / stick (if exists) END START TPG D CUT C B TPG A F ORA E Testee Stick Tester Stick TPG D C CUT B A TPG F ORA E TPG D CUT C TPG B CUT A TPG F ORA E HD-BIST [Suthar & Dutt, GLSVLSI’05] Theorem: = prob. of shuffled TPG skipping a test vector. = prob. of normal TPG skipping a test vector. p = prob. of a PLB being faulty.

HD-BISTer is compared with previous best online BIST techniques: STAR BISTer proposed by [M. Abramovici et. al., ITC’00] and BISTer-1 HD_3 -> HD-BISTer with TPG shuffling HD_1 -> HD-BISTer without TPG shuffling. FAULT COVERAGE: HD-BIST Experimental Results

Mixed-BIST: Interconnect BIST Stages I-BIST [Suthar & Dutt, DATE’06] Approach: 1. Global Testing: First isolate the possible fault locations to a small set of interconnects in very few configurations -> Suspect Set 2.Detailed Testing: Then diagnose interconnects of suspect set for faults using divide-&-conquer and in the final iteration by comparison to known fault- free interconnects Global Testing (1/5 configs)

I-BIST: Results Fault coverage (diagnosability) versus fault density Theoretical Results: Theorem: I-BIST has 100% guaranteed fault detectability in the presence of multiple faults – a first Theorem: I-BIST has 100% guaranteed fault detectability in the presence of multiple faults – a first I-BIST has the fewest configurations—5—per WUT-set in global testing I-BIST has the fewest configurations—5—per WUT-set in global testing I-BIST has the fewest # of test vectors—3—per WUT-set testing phase I-BIST has the fewest # of test vectors—3—per WUT-set testing phase Empirical Results:

Mixed-BIST– Summary of Techniques Our Mixed-BIST (M-BIST) approach attempts to significantly reduce these negative effects via –a careful application of iterative bootstrapping –interleaving of various stages of I-BIST and HD-BIST First phase – IB w/ TMR Phase Test ckt. rqd. for phase Non TMR’ed

Mixed BIST: Combining & Interleaving IB, I-BIST & HD-BIST

Comparison of PLB and interconnect testing in M-BIST (without fault-free assumptions) v/s HD-BIST (with fault-free assumptions) & I-BIST (with fault-free assumptions) Simulation Results – Fault Coverage Fault coverage – random faults M-BIST v/s HD-BIST (w/ f-free assumptions)M-BIST v/s I-BIST (w/ f-free assumptions) 2 % difference 1.5 % difference

False positive results – random faults False positives – fault-free components incorrectly diagnosed as faulty. -- measured as a percentage of faults inserted. Simulation Results – False Positives 40% 200% 5 % 0% M-BIST v/s HD-BIST (w/ f-free assumptions)M-BIST v/s I-BIST (w/ f-free assumptions)

Conclusions Goal: Mixed PLB and Interconnect BIST that does not require any fault-free assumptions in order to: – –improve diagnosability and reduce false positives –in the presence of clustered and high density faults in both PLBs and interconnects in different test and fault tolerance domains Introduced the novel concept of general iterative bootstrapping for this purpose that can be used in different test and fault tolerance domains Analyzed the mathematical conditions for improved diagnosis using iterative bootstrapping Applied iterative bootstrapping in novel ways (TMR, shuffled TPGs, TPGs w/o i/o faults) to develop a Mixed BISTer M-BIST sans fault-free assumptions Achieved our aim of accurate PLB and interconnect diagnosis Future Work: Built-in controller for diagnosis and reconfiguration

THANK YOU

Built-In Self-Test in FPGAs—On-Line & Off-Line CIRCUIT ROTE (ROving TEster) Two column left spare for ROTE; one for fault reconfiguration ROTE roves across the FPGA SPARE COLUMN CIRCUIT SPARE COLUMN TPG - Test Pattern Generator ORA - Output Response Analyser CUT - Cells Under Test BISTer: WUT - Wires Under Test WUT TC CO CT OC In each session diff. PLBs act as CUTs, TPG and ORA. TPG CUT ORA Pass / fail WUT

Mixed-BIST: Interconnect BIST Stages (contd) Global testingDetailed testing—Divide-&-Conquer Switch stuck-closed A OO O O O Suspect interconnect Fault-free interconnect

M-BISTer (Mixed-BISTer):