16 February 2011Ian Brawn1 The High Speed Demonstrator and Slice Demonstrator Programme The Proposed High-Speed Demonstrator –Overview –Design Methodology –Cost Summary

16 February 2011Ian Brawn2 Background The problems of data transport and sharing in the L1Calo Phase-2 processor are minimised if we use multi-Gb/s data links –We have assumed we’ll be using speed in this order Signals in multi-Gb/s range present challenge to PCB design –Reflections, Rising edge of signals is comparable to physical size of components, vias, etc  distributed rather than lumped system –Crosstalk, –High-frequency attenuation, –Differential skew… Require carefully controlled Placement of components and routing of tracks

16 February 2011Ian Brawn3 Multi-Gb/s Experience In industry it is standard to model and simulate PCBs during the design process to ensure required signal integrity is acheived In UK we have limited experience of multi-Gb/s design –At RAL, PCB Design Office have built a few boards in Gb/s range using design rules eg, XFEL FEM 3.25 Gb/s, short links –We have no experience of PCB simulation Within wider community, CERN have a working group looking at PCB simulation If we are to successfully use multi-Gb/s links in the L1Calo processor we need to educate ourselves (and the Design Office) –Best to do this on a dedicated demonstrator –Not one that has lots of expensive FPGAs

16 February 2011Ian Brawn4 Design Methodology Real goal of this programme is not to produce hardware Producing a board that does/doesn't work at multi-Gb/s will tell us little if we don't understand how we got there. Real goal is to equip ourselves with capability of producing working multi- Gb/s PCBs in reliable fashion: –Simulation –Extraction of electrical model from hardware –Feedback of electrical model into simulation –Learn from our successes and failures

16 February 2011Ian Brawn5 Conceptual Design FPGA used as a source/sink of multi-Gb/s serial signals –10 Gb/s or 5 Gb/s speeds considered Aim is to allow as many different path types as possible to be tested –FPGA–transceiver –FPGA–RTM–transceiver –FPGA–Crosspoint switch–FPGA, etc Implement paths of a variety of lengths & vias Propose building (at least) two of these modules, to enable backplane transmission FPGA Cross- point Switch Op. TX Op. RX Demonstrator ModuleRTM ATCA backplane Mezzanine a b c d e f g h k l m n

16 February 2011Ian Brawn6 Infrastructure Obviously desirable to use the same standard in the final system and demonstrator. Parallel bus architectures, including VME, are not candidates for the L1Calo Phase 2 Trigger crate Of the serial backplanes available, ATCA seems the best candidate –Serial, point-to-point communication across backplane –High availability, scalability, flexibility –Massive I/O capability –Telecoms standard –Widely used in industry –Gaining wide support in our community

16 February 2011Ian Brawn7 Testing Conducted using ESS 20 GHz scope: 86100C DCA-J Oscilloscope Mainframe Software: –Jitter measurements –Enhanced impedance and S-parameter –Advanced waveform analysis Plug-in Modules: –9 GHz optical /20 GHz electrical sampling module –Differential TDR module including 6 GHz TDR probe –20 GHz Dual channel Electrical module –Clock recovery module (optical and electrical 50mb/s – 7.1 Gb/s Other enhancements: –Enhanced trigger 13 GHz BW –Filters for waveform characterisation –Adjustable loop bandwidth

16 February 2011Ian Brawn8 Costing – 10 Gb/s option

16 February 2011Ian Brawn9 Impementation 5 Gb/s links can be implemented by a Virtex5 device 10 Gb/s links require a high-end V6 device (XC6VHX255T) Preference is to impement 10 Gb/s but it may be necessary to build 5 Gb/s board first –Availability of required Xilinx device is uncertain We’ve had trouble extracting V6 quotes from Silica (quote used here is from Silica web site) We could consider ALTERA…. A two-stage demonstrator programme? –Demonstrator 1: 5 Gb/s, to proceed immediately –Demonstrator 2: 10 Gb/s, GBT, additional functionality for a slice demonstrator programme Timescale: first demonstrator ready for testing Q4 2011

16 February 2011Ian Brawn10 Summary The proposed L1Calo programme requires that we understand how to manufacture multi-Gb/s PCBs reliably, and it is to our benefit if this knowledge is acquired by as many of the institutes as possible. In the UK we propose to build a High-Speed demonstrator to educate ourselves (and RAL PCB Design Office) in multi-Gb/s PCB design Functionaly the module will be simple; it will be a test bench for us to investigate the behaviour of multi-Gb/s signals This will be the first step in a demonstrator programme that we look forward to defining in the near future.