Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Working with Buses & Interconnects April 5, 2007 W. Rhett Davis NC State University

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 2 Today’s Lecture l Introduction l AMBA Peripheral Bus (APB) l AMBA High-Performance Bus (AHB) l AMBA Extensible Interconnect (AXI)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 3 Why do we care? l What is a Bus? l What is an Interconnect? l Why do we use them?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 4 Our Question l Which bus or interconnect should we use? The answer depends on the following: » What IP blocks do we have and what do they work with? » How many ports do we need? » What kind of overhead can we permit? –Throughput –Area –Power

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 5 Bus & Interconnect Standards l AMBA from ARM l Wishbone from OpenCores.org l CoreConnect from IBM l Sonics “Silicon Backplane” We’ll focus on AMBA in this class, because it’s the one our simulator models.

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 6 AMBA Introduction l Advanced Microcontroller Bus Architecture (AMBA), created by ARM as an interface for their microprocessors. l Easy to obtain documentation (free download) and can be used without royalties. l Very common in commercial SoC’s (e.g. Qualcomm Multimedia Cellphone SoC) l AMBA 2.0 released in 1999, includes APB and AHB l AMBA 3.0 released in 2003, includes AXI

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 7 AMBA 2.0 System-Level View Source: AMBA Specification, Rev. 2.0

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 8 Today’s Lecture l Introduction l AMBA Peripheral Bus (APB) l AMBA High-Performance Bus (AHB) l AMBA Extensible Interconnect (AXI)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 9 APB Introduction l Low overhead – only 4 control signals l Only one master is allowed l Three states: IDLE, SETUP, and ENABLE l Slave is non-responsive: Transfer always takes 2 cycles » Makes timing easy to design: data is always latched between the two cycles

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 10 APB Read Transaction l Transaction takes 2 cycles: SETUP & ENABLE

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 11 APB Write Transaction

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 12 APB Performance l If AHB is “high performance” than APB must be “low performance”. What does that mean? l If we were to connect an SDRAM as an APB slave from the previous lecture, what would our minimum bus clock period be?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 13 Today’s Lecture l Introduction l AMBA Peripheral Bus (APB) l AMBA High-Performance Bus (AHB) l AMBA Extensible Interconnect (AXI)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 14 AHB Introduction l Larger overhead – ~27 control signals l Up to 15 masters allowed l Split Transaction phases: Address, Data (Pipelined) l HREADY signal allows insertion of wait- states

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 15 AHB Architecture l Central MUX is used, rather than a bus l Achieves smaller delays than a single wire w/ tri-state buffers Source: AMBA Specification, Rev. 2.0

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 16 AHB Split-Transaction Bus l Address preceeds data by one cycle l Mimics SDRAM operation, achieves greater data bandwidth Source: AMBA Specification, Rev. 2.0

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 17 Multiple Transactions w/ AHB l Addresses are pipelined to improve memory efficiency l HREADY from slave allows insertion of wait states Source: AMBA Specification, Rev. 2.0

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 18 AHB Burst Operation l Bursts with lengths up to 32 are allowed l What would happen if an incrementing burst read to a DRAM row boundary?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 19 AHB Access Grant Mechanism l Bus arbitration takes extra cycles Source: AMBA Specification, Rev. 2.0

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 20 Today’s Lecture l Introduction l AMBA Peripheral Bus (APB) l AMBA High-Performance Bus (AHB) l AMBA Extensible Interconnect (AXI)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 21 AXI Introduction l Larger overhead – ~77 control signals l Up to 16 masters allowed l 5 separate channels for address, data, and responses l Not so much of an interconnect specification as a protocol (interconnect architecture is left unspecified)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 22 Multi-Channel Support l Address, Data, and Response split between channels, rather than phases l Allows simultaneous reads and writes Source: AMBA AXI Protocol Specification

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 23 AXI Read Transactions l Up to 16 transactions can be queued at once

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 24 Multi-Layer Connectivity l PL300 Interconnect is implemented as a crossbar: l Multiple masters can talk to multiple slaves simultaneously Source: PL300 Technical Reference Manual

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 25 Comparison of AMBA Bus Types APBAHBAXI / PL300 ProcessorsallARM7,9,10ARM11 Control Signals42777 No. of Masters No. of Slaves Interconnect Type Central MUX? Central MUX Crossbar w/ 5 channels PhasesSetup, Enable Bus request, Address, Data Address, Data, Response Xact. Depth1216 Burst Lengths Simultaneous Read & Write no yes