TRIGGER DELAY 100µs

G. Gräwer AB/BT/ECLBDS Trigger Delay2 The trigger delay is a back-up system that generates an asynchronous dump trigger for MKD and MKB in case of problems with the synchronous dump trigger. Design goals are to make a system that is stand-alone, simple and reliable. Stand–alone means that the system is completely self- contained. Its function is not affected by any external condition. Simplicity means to minimise number of components for the critical part of the circuit. Requirements

G. Gräwer AB/BT/ECLBDS Trigger Delay3 Block diagram

G. Gräwer AB/BT/ECLBDS Trigger Delay4 General description The trigger delay generates an output pulse 100µs after the input trigger The trigger delay unit has got two internal 24V power supplies. If one of them fails it continues working with the other one and a warning signal is generated for the PLC. The faulty power supply should be replaced at the next possible occasion. If both power supplies fail or in case of mains failure supply voltage is maintained by internal capacitors. The unit still remains operational for several minutes (up to 30min). In case of a fault in the trigger delay unit the interlock circuit generates an error signal for the PLC. There are three possible faults that can cause an error: Input disconnected. Output disconnected. Low voltage of oscillator capacitor.

G. Gräwer AB/BT/ECLBDS Trigger Delay5 Schematic of trigger delay

G. Gräwer AB/BT/ECLBDS Trigger Delay6 Main circuit The trigger delay circuit is completely analogue. The semiconductors used in the critical part of the circuit are one thyristor Q 1, one MOSFET M 1 and several diodes. The delay time is determined by one period of an LC oscillator L 1 and C 7. A trigger pulse at the input triggers Q 1. For the first half of the oscillation the current flows through Q 1 until the zero crossing. For the second half of the oscillation the current changes direction and flows through the diode D 14 while Q 1 is turned off. At the end of the oscillation Q 1 blocks the voltage VT. The rising edge of VT turn on M 1 and this generates the output trigger pulse. Principle of operation

G. Gräwer AB/BT/ECLBDS Trigger Delay7 Interlock circuit The Interlock circuit monitors the internal 24V supply voltages, the voltage VT at Q 1 and the interlock loop. If one of the supply voltages fails a warning signal is generated. If VT stays low for too long, the interlock loop is broken or the input is disconnected an error signal is generated. The cable from the trigger delay unit to the retrigger boxes contains two pairs of wires. One for the trigger signal and one for the interlock loop. At the end of the cable the interlock loop must be shorted. This is to make sure that the trigger cable is properly connected. Principle of operation

G. Gräwer AB/BT/ECLBDS Trigger Delay8 Oscillator current Oscillator Voltage Trigger in Trigger out VT Waveforms

G. Gräwer AB/BT/ECLBDS Trigger Delay9 Input fault detection

G. Gräwer AB/BT/ECLBDS Trigger Delay10 Schematic of interlock circuit

G. Gräwer AB/BT/ECLBDS Trigger Delay11 Trigger delay PCB