IV&V Facility Research and Development of Deployable IV&V Methods for FPGA Applications Northrop Grumman, KeyLogic Systems, Mountain State Information.

Slides:



Advertisements
Similar presentations
Design Implementation Full Custom ICs, ASICs & PLDs ETEG 431 SG ASIC: Application Specific Integrated Circuit PLD: Programmable Logic Device FPGA: Field.
Advertisements

FPGA (Field Programmable Gate Array)
Software Modeling SWE5441 Lecture 3 Eng. Mohammed Timraz
University Of Vaasa Telecommunications Engineering Automation Seminar Signal Generator By Tibebu Sime 13 th December 2011.
Reliable SW/HW Co-Design for Wireless Communication System Integrating the Spin Model Checker and Celoxica's DK Suite Stefanos Skoulaxinos School of EPS.
PRJ270: Essentials of Rational Unified Process
FPGA Design Flow Design Circuit Simulation Implementation Programming.
© Copyright Richard W. Selby and Northrop Grumman Corporation. All rights reserved. 0 Process Synchronization and Stabilization February 2007 Rick.
L4-1-S1 UML Overview © M.E. Fayad SJSU -- CmpE Software Architectures Dr. M.E. Fayad, Professor Computer Engineering Department, Room #283I.
Verification and Validation of Programmable Logic Devices James A. Cercone Ph.D., P.E.,James A. Cercone Ph.D., P.E., Chair and Professor of Computer ScienceChair.
1 McGraw-Hill/Irwin Copyright © 2004, The McGraw-Hill Companies, Inc. All rights reserved. Information Systems Development – The System Approach 1. “System.
1 Chapter 7 Design Implementation. 2 Overview 3 Main Steps of an FPGA Design ’ s Implementation Design architecture Defining the structure, interface.
CS 151 Digital Systems Design Lecture 38 Programmable Logic.
Copyright © 2004 by South-Western, a division of Thomson Learning, Inc. All rights reserved. Developed by Cool Pictures and MultiMedia Presentations Copyright.
Mission/Vision Statement Deliver high performance COTS products for the most challenging applications. We help our customers reduce project risk by providing.
(1) Introduction © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.
2 Outline Digital music The power of FPGA The “DigitalSynth” project –Hardware –Software Conclusion Demo.
Implementation of Digital Front End Processing Algorithms with Portability Across Multiple Processing Platforms September 20-21, 2011 John Holland, Jeremy.
N A managed approach to planning and controlling the implementation of complex application software. n A flexible tool kit, designed to support the Project.
Effective Methods for Software and Systems Integration
International Master of Science Program in System-on-Chip (SoC) Design at KTH SoC Masters Axel Jantsch Royal Institute of.
Appendix 2 Automated Tools for Systems Development © 2006 ITT Educational Services Inc. SE350 System Analysis for Software Engineers: Unit 2 Slide 1.
1 IBM Software Group ® Mastering Object-Oriented Analysis and Design with UML 2.0 Module 1: Best Practices of Software Engineering.
Chapter 7: The 30 elements of systems engineering
Research Heaven, West Virginia Verification and Validation of Adaptive Systems Online Failure Detection and Identification for IFCS through Statistical.
CIT UPES | Sept 2013 | Unified Modeling Language - UML.
Signal Intel CDC Columbia, SC 11WW14 Hendrick, Matt R Gregory, Adam
© 2007 Pearson Education, Inc. Publishing as Pearson Addison-Wesley 1 A Discipline of Software Design.
1 3-General Purpose Processors: Altera Nios II 2 Altera Nios II processor A 32-bit soft core processor from Altera Comes in three cores: Fast, Standard,
T. Dawson, TASC 9/11/13 Use of a Technical Reference in NASA IV&V.
CS 303 Logic & Digital System Design. Logic & Digital System Design Examles of Usage –Vending Machines –Communication System –μ-Processors –Traffic controls.
MD Digital Government Summit, June 26, Maryland Project Management Oversight & System Development Life Cycle (SDLC) Robert Krauss MD Digital Government.
Slide 1V&V 10/2002 Software Quality Assurance Dr. Linda H. Rosenberg Assistant Director For Information Sciences Goddard Space Flight Center, NASA
Lecture 2 1 ECE 412: Microcomputer Laboratory Lecture 2: Design Methodologies.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
CS 3610: Software Engineering – Fall 2009 Dr. Hisham Haddad – CSIS Dept. Chapter 6 System Engineering Overview of System Engineering.
Robotics & Engineering Design Projective Management Chin-Sung Lin Eleanor Roosevelt High School.
© 2004 Mercury Computer Systems, Inc. FPGAs & Software Components Graham Bardouleau & Jim Kulp Mercury Computer Systems, Inc. High Performance Embedded.
Microelectronic Systems Institute Leandro Soares Indrusiak Manfred Glesner Ricardo Reis Lookup-based Remote Laboratory for FPGA Digital Design Prototyping.
Programmable Logic Educating Assurance Engineers NASA Glenn Research Center Kalynnda Berens (PI) Jackie Somos (Course designer)
Unified Modeling Language* Keng Siau University of Nebraska-Lincoln *Adapted from “Software Architecture and the UML” by Grady Booch.
L6-S1 UML Overview 2003 SJSU -- CmpE Advanced Object-Oriented Analysis & Design Dr. M.E. Fayad, Professor Computer Engineering Department, Room #283I College.
“Politehnica” University of Timisoara Course No. 2: Static and Dynamic Configurable Systems (paper by Sanchez, Sipper, Haenni, Beuchat, Stauffer, Uribe)
2D/3D Integration Challenges: Dynamic Reconfiguration and Design for Reuse.
The Rational Unified Process 1 EECS810: Software Engineering.
Architecture View Models A model is a complete, simplified description of a system from a particular perspective or viewpoint. There is no single view.
Programmable Logic Device Architectures
Completing the Loop: Linking Software Features to Failures 31 July 2003 Copyright © 2003, Mountain State Information Systems, Inc. All rights reserved.
Creating Security using Software and Hardware Bradley Herrup CS297- Security and Programming Languages.
Software Engineering Lecture 10: System Engineering.
Completing the Loop: Linking Software Features to Failures 20 July 2004 Copyright © 2004, Mountain State Information Systems, Inc. All rights reserved.
Lecture Exam 1 Study Guide Albert Kalim. Chapter 1: Computer Basics 1. Explain why it’s essential to learn about computers today. 2. Discuss several ways.
ISIS Project Status Report May 18, 2006 Prepared by MAXIMUS, Inc Education Systems Division for the ABT Committee.
SAS_06_FPGA_NGIT1 Research and Development of Deployable IV&V Methods for FPGA Applications Northrop Grumman, KeyLogic Systems, Mountain State Information.
CHANGE MANAGEMENT - PART 2 MODULE 7
© Copyright 2003 Frost & Sullivan. All Rights Reserved. World Radio Frequency Identification (RFID) Middleware Markets Soumilya Banerjee, Research Analyst,
1 DEPLOYMENT AND OPERATIONS MODULE 23 ECM SPECIALIST COURSE 1 Copyright AIIM.
9/4/2001 ECE 551 Fall ECE Digital System Design & Synthesis Lecture 1 - Introduction  Overview oCourse Introduction oOverview of Contemporary.
Multiprocessing.
VLSI Tarik Booker.
Introduction to VLSI ASIC Design and Technology
EEE2135 Digital Logic Design Chapter 1. Introduction
FPGA BASED SPEED CONTROL OF BLDC MOTOR USING SINUSOIDAL PWM
Overview of System Engineering
cFS Workshop Product Management
تراشه ها ي منطقي برنامه پذ ير
CS 8532: Advanced Software Engineering
HIGH LEVEL SYNTHESIS.
Physical Implementation
♪ Embedded System Design: Synthesizing Music Using Programmable Logic
Presentation transcript:

IV&V Facility Research and Development of Deployable IV&V Methods for FPGA Applications Northrop Grumman, KeyLogic Systems, Mountain State Information Systems, Inc., The University of Montana and West Virginia University July 20, 2006

IV&V Facility Project Need What are the methods/procedures/standards for analysis of FPGAs? –Provide field proven Work Instruction to the IV&V Practitioner Establish IV&V’s role in the analysis of FPGAs –Develop an overall IV&V strategy and position –Address static and dynamic needs/methods across full life-cycle FPGAs are playing increasingly prominent roles in NASA missions –They are partially hardware and partially software –They are attractive because they do not have the month(s) lag time associated with manufacturing custom chips but provide many of the same features FPGA IV&V methods are accurately documented and communicated High speed software functions are evolving to FPGAs in NASA missions. IV&V of these devices is important to the agency to maximize mission success. High speed software functions are evolving to FPGAs in NASA missions. IV&V of these devices is important to the agency to maximize mission success.

IV&V Facility What are challenges in FPGA IV&V? Effective FPGA IV&V addresses both the abstract representation and the physical implementation Effective FPGA IV&V addresses both the abstract representation and the physical implementation Design Method (abstract representation) Implementation (Physical Representation) Typical Speed of Operation SOFTWARECOMPUTER 10’s Hz FIRMWAREMICROPROCESSOR MICROCODESEQUENCER DIGITAL DESIGNCHIPS/DIGITAL CIRCUITS RF DESIGNRADIOS/RF CIRCUITS ANALOGTRANSISTORSContinuous MHz GHz KHz Some challenges here different than FSW: Timing, Loading, Integrated package (circuit/software) --  requires dynamic IV&V analysis methods FPGAs straddle: Abstract representations like SW (HDL) Physical implementations like Digital Design

IV&V Facility Approach This is a “standard initiative” with 5 steps: 1. Surveying and cataloging existing FPGA applications 2. Concept/Requirements Phase: –Methods for Concept/Requirements analysis –Identify potential methods for full-lifecycle analysis 3. Design/Implementation Phase: –Dynamic analysis including functional and timing simulations at the unit level –Envisioned work instructions build on successful MRO analysis methods 4. Test Phase: –Define the types of design and implementation validation that can be practically accomplished via subsystem testing 5. Project transference: Continue with pilot and other projects Steps 1-4 occur in Year 1, and Step 5 in Year 2