Multiprocessor SoC integration Method: A Case Study on Nexperia, Li Bin, Mengtian Rong Presented by Pei-Wei Li

Outline Introduction Introduction SoC Methodology Overview SoC Methodology Overview MultiProcessor SoC trends MultiProcessor SoC trends Interconnection Network Architecture Interconnection Network Architecture A Case Study: Nexperia 8500 Architecture A Case Study: Nexperia 8500 Architecture Performance evaluation Performance evaluation Conclusion Conclusion Comment Comment

Introduction SoC design technology has significant progress, more and more advanced processors use this method. SoC design technology has significant progress, more and more advanced processors use this method. MPSoC is simply a system-on-chip that contains multiple instruction-set processors (CPUs). MPSoC is simply a system-on-chip that contains multiple instruction-set processors (CPUs).

Introduction This paper studies how SoC technology can be use to design processor, and embedded multiprocessor. This paper studies how SoC technology can be use to design processor, and embedded multiprocessor. There are many kinds of MPSoC products at market, Philips Nexperia8500 is an example. There are many kinds of MPSoC products at market, Philips Nexperia8500 is an example. Finally, the results of Nexperia8500 processor performance are presented. Finally, the results of Nexperia8500 processor performance are presented.

SoC Methodology Overview Component-based SoC design: – – It starts with a set of components and provides a set of primitives to build application-specific architectures and communication links. The key idea is to increase the abstraction level when designing component interconnections. It may provide a considerable reduction of design time for hardware/software communication refinement and component integration and may facilitate IP reuse.

MultiProcessor SoC trends

The topologies for interconnecting multiple processors consist of simple bus structures, dual-ported memories linking processors, and on-chip processor communication networks. Design-space exploration through the simulation of various multi-processor system designs is essential to choosing the right connection topology in these systems.

Interconnection Network Architecture The shared-bus based communication architecture topology is popular choices for on-chip communication between components. The architecture usually consists of several shared busses interconnected by bridges to form a hierarchy. Different levels of the hierarchy correspond to the varying communication bandwidth requirement of SoC components.

A Case Study: Nexperia 8500 Architecture

Performance evaluation TM32 is a high performance very long instruction word (VLIW) processor specially optimized for communication or multimedia signal applications. It can issue at 5 instructions at the same time. The maximum clock frequency is 400MHZ. It has 128×32-bit general-purpose registers and on-chip hardware support for audio- video I/O.

Performance evaluation

Conclusion In this paper, we have presented the micro- architecture of the Nexperia8500. TM32 has more better performance because it has more registers. MPSoC integration enables large improvements in processor performance, cost/performance, floor space, and total power consumed over previous processor.

Comment English grammar errors English grammar errors Related works are not presented. Related works are not presented. The results of Nexperia 8500 processor performance are from Philips Semiconductor. The results of Nexperia 8500 processor performance are from Philips Semiconductor.