MICRO-CONTROLLER MOTOROLA HCS12 Interrupts Mechatronics Department Faculty of Engineering Ain Shams University

Interrupts Handling Sources of interrupts Interrupt service routines Interruption mechanism Interrupt control registers Real-time interrupts

Interrupts Sources of interrupts  Maskable and non-maskable external interrupt pins.  Reset.  Real-Time Interrupt (RTI).  A 16-channel 10-bit A/D converter.  Enhanced Capture Timer (ECT) I/O on PortT.  A watchdog timer (COP).  A clock monitor.  Software interrupts

Interrupts Interrupt Service Routines  The script to be executed when an interrupt occurs.  It can be labeled by any label.  Never forget to write RTI at the end of interrupt service routine to pull back the CPU status and return address from the stack.

Interrupts Interruption mechanism 1. Saving the program counter value. 2. Saving the CPU status in the stack. 3. Identifying the source of the interrupt. 4. Fetch the starting address of the corresponding interrupt service routine. 5. Executing the interrupt service routine. 6. Restoring the CPU status from the stack. 7. Restoring the program counter from the stack. 8. Resuming the interrupted program.

Interrupts Interruption mechanism Masking interrupts:  The I and X bits in the CCR act globally. (setting the I bit disables external IRQ and other maskable internal interrupt sources).  CLI is the instruction used to clear the interrupt flag.  ANDCC#% – is also used to clear the interrupt flag.  ORCC#% – is used to enable interrupts by setting the interrupt flag.  If the ISR resets the I bit - not recommended - because it may cause nested interrupts.

Interrupts Interruption Priorities Six sources are not maskable: (listed according to priority) 1. Power-on reset (POR) or RESET pin 2. Clock monitor reset 3. Computer operating properly (COP) watchdog reset 4. Unimplemented instruction trap 5. Software interrupt instruction (SWI) 6. XIRQ signal if X bit in CCR = 0 The remaining sources are maskable, and any one of them can be given priority over other maskable interrupts.

Interrupts Interrupt control registers Interrupt Control Register (INTCR) Highest Priority Control Register (HPRIO)

Interrupts Interrupt control registers Interrupt Control Register (INTCR)

Interrupts Interrupt control registers Highest Priority Control Register (HPRIO) We distinct between interrupt sources with their Vectors This byte includes the vector of the interrupt with highest priority. We distinct between interrupt sources with their Vectors This byte includes the vector of the interrupt with highest priority.

Interrupts Interrupts vectors

Interrupts Interrupts vectors definition

Eng. Mohamed Mahmoud Hamdy Eng. Mostafa Ahmed Arafa Eng. Abd Allah Mahmoud Selim Prepared by: