ENG2410 Digital Design LAB #7 LAB #7 Sequential Logic Design “Sequence Recognizer” Using both Schematic Capture and VHDL
ENG241/Lab #72 Lab Objectives Reinforce concepts we learnt about sequential circuits in class. Understand sequential circuit design flow: In this lab you will design a 4-bit Sequence Recognizer using both: 1.Schematic Capture and 2.VHDL
ENG241/Lab #73 Sequence Recognizer Sequence recognizer is used to detect a specific pattern in a serial input. You are required to design a circuit that detects the pattern “1101”
ENG241/Lab #74 The Sequence Recognizer Steps: Construct the state diagram of a Moore Machine. Derive the state transition table. Design the sequential machine using D Flip Flops. Use Schematic Capture to enter your design. Redesign using VHDL.
ENG241/Lab #75 Switch De-bouncing The switches and push buttons on the FPGA NEXYS3 board might experience oscillations due to the nature of mechanical keys: One way to de-bounce a key is to introduce a delay until all the oscillations disappear. We provide you with VHDL Code to solve the problem.
ENG241/Lab #76 VHDL Code:Switch De-bouncing 1. Create a new project (Call it DebounceModule) 2. Use the VHDL provided on the resources section on Lab #7. 3. Synthesize the VHDL code and transform it into a symbol that can be used in any schematics 4. The connectivity is as shown below: Debouncing Circuit (Clock on FPGA) (Push Button on FPGA) Your Circuit push_bt cclk debounce_out
Lab Report Title Page – Group # and Names Problem Statement System Overview and Justification of Design State Diagram State Transition Table, Circuit, Schematic VHDL Code (Include COMMENTS!) Sequence Recognizer Sequence Recognizer Simulation Waveform Problems Encountered and Recommendation ENG241/Lab #77
Academic Misconduct Reports and demos are submitted as a group, but it is a SINGLE group effort You may talk with other groups but sharing codes or reports is NOT ALLOWED Copying reports from previous years is also NOT ALLOWED If we find copying we are REQUIRED to report it