Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL A Versatile Carrier Board and Associated Timer Module Applications Work supported by, the Joint Technology Office, the Office of Naval Research, the Air Force Research Laboratory, Army Night Vision Laboratory, the Commonwealth of Virginia, U.S. Dept. of Energy under contract DE-AC05-84-ER40150 and the Laser Processing Consortium R. Evans, A. Grippo, K. Jordan Thomas Jefferson National Accelerator Facility Presented by Richard K. Evans

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Presentation Overview: * Short survey of our approach to providing application specific instrumentation and controls * Quick look at the FEL User Facility at Jefferson Lab * Description of the 6U Versatile Carrier Board Design * Module foot-print and basic function add-on modules * The 4 Channel Programmable Timer Board * Applications of the Timer Boards in FEL Systems * Future of these modular designs * Acknowledgements and Thanks

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL The Free Electron Laser (FEL) User Facility At Jefferson Lab The Free Electron Laser (FEL) User Facility At Jefferson Lab FEL User FacilityFirst Floor Layout showing 7+ User Labs CEBAF at Jefferson Lab in Newport News, Va. USA

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Our Approach To Providing The FEL Control Systems * Copy as many CEBAF system designs as possible. (i.e. LINAC, RF, LLRF, BPMs, Magnet Power Supplies, Vacuum, etc...) * “New system designs” reserved for systems which are: a) unique to the FEL (i.e. LPSS, OTS, Multipass BPMs, DLPC) b) where previous solutions are obsolete (BLMs, Viewer Ctrl) c) where significant advantages are gained by using a new approach. (i.e. MPS, BPMs, ) * “As-Needed” Solutions to System Integration and Evolving System Requirements driven by the experiences gained by operating the FEL. (Timing System (OBPMs), User Support,... “Application Specific” I&C) And we all know... “The Devil is in the details”

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Results of a self-survey of various in-house solutions * Custom Chassis and Box Designs are not efficient. (AC/DC power issues, bulky, not very space efficient, cooling issues) * Still designing VME but... “the writing is on the wall” So..., Lets standardize the widget cards into a family of GENERAL PURPOSE MODULES which can be used on a generic (versatile) 6U form factor carrier card. * Most VME crates have at least 1 “one-of-a-kind” widget Many of the VME cards built do not need to ‘talk’ to the VME Bus The convenience of the crate Power Supply allows for simple solutions The 6U form factor provided adequate space for every widget function Simple Digital I/O S&H, ADC and DAC Timing/Delay Generators Simple PLD logic 50/75 ohm Signal Distribution Logic Conversion (24V, TTL, etc...) Relay Interlocks and Digital Isolation Fiber Optic Interfaces (Heartbeat to Logic) Embedded IOCs are will be commonplace in the very near future CAN bus I/O is an under-utilized technology (by us)

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL * P1 P2 Carrier Board Design Carrier Board Design - Standard VME P1 & P2 - P2 has 64 user def. pins * 6U Form Factor * Board space is divided into 4 equal sections - Each Module gets 16 I/O from P2 onto a 40 pin Conn. - Each Side has a 16 pin Local-Bus (A & B busses) * * * * - Bus “A” (*) has a set of 16 lines shared I/O and 8 distributed pins for various power * * * * - Bus “B” (*) has a set of 16 lines shared I/O and 8 distributed pins for serial communications - A P3 connector allows front to back throughput P3 - Module A/Slot A is “Special” because it has access to a VME Interface connector (*)

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Module foot-print... and... some basic function add-on modules Simple Digital I/O ADCs and DACs Timing/Delay Generators Simple PLD logic 50/75 ohm Signal Distribution Logic Conversion (24V, TTL, etc...) Relay Interlocks and Digital Isolation Fiber Optics Interfaces (Heartbeat to Logic)

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Module foot-print... and... some basic function add-on modules

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Finished Carrier Board Block Diagram and PCB comparison

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL 6U - 12 Channel BLM Card with the ‘Modular’ VME Interface I/O

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL FEL Video Crosspoint Board with “Modular” Interface Socket FEL Video Crosspoint Board with “Modular” Interface Socket

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL 6U Carrier Board as a 4 Ch. Programmable Timer System 6U Carrier Board as a 4 Ch. Programmable Timer System

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Module Based, 4 Ch. Programmable Timer System EPICS Control

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Applications of the Timer Boards in FEL Systems Drive Laser Pulse Controller (DLPC) Providing Highly Configurable Digital Timing Control of the Drive Laser’s Electro-Optical Cells allows us to: Drive Laser Pulse Controller (DLPC) Providing Highly Configurable Digital Timing Control of the Drive Laser’s Electro-Optical Cells allows us to: Macropulse Pulse Repetition Rate Macropulse Pulse Repetition Rate Macropulse Duty Factor (Pulse Width) Macropulse Duty Factor (Pulse Width) A/C Line Lock (60Hz, 30Hz, 20Hz,..., 0.5 Hz, etc...) A/C Line Lock (60Hz, 30Hz, 20Hz,..., 0.5 Hz, etc...) Synchronize with the M.O. (at MHz) Synchronize with the M.O. (at MHz) Auto Phase Rotate (Line Phase, i.e. 60Hz) Auto Phase Rotate (Line Phase, i.e. 60Hz) Asynchronous Repetition Rates (f < 10MHz) Asynchronous Repetition Rates (f < 10MHz) Pre-trigger Delay Pre-trigger Delay (Mechanical Shutter, Happek, M55,...) Beam Sync locked to M.O. External Trigger for Beam Pulse N-Pulse mode from EPICS

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Applications of the Timer Boards in FEL Systems (cont...) Multipass BPM timing at MHz (M.O.=1497 MHz) / (40) / (2 5 ) = (M.O. / 1280) Multipass BPM timing at MHz (M.O.=1497 MHz) / (40) / (2 5 ) = (M.O. / 1280) Path Length = m  ~433ns multipass delay

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Applications of the Timer Boards in FEL Systems (cont...) Multipass BPM timing at MHz (M.O.=1497 MHz) / (40) / (2 5 ) = (M.O. / 1280) Multipass BPM timing at MHz (M.O.=1497 MHz) / (40) / (2 5 ) = (M.O. / 1280)

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL Applications of the Timer Boards in FEL Systems (cont...) Multipass BPM timing at MHz (M.O.=1497 MHz) / (40) / (2 5 ) = (M.O. / 1280) Multipass BPM timing at MHz (M.O.=1497 MHz) / (40) / (2 5 ) = (M.O. / 1280)

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL The Future of these modular designs... The Future of these modular designs... This versatile system of boards has been designed with two primary purposes in mind: - 1) To address aspects of system integration that has “slipped between the cracks” and has no formal solution and to standardize these components. - 2) To minimize the overhead in testing out new ideas and providing solutions which can be provided early while the formal systems are designed. This versatile system of boards has been designed with two primary purposes in mind: - 1) To address aspects of system integration that has “slipped between the cracks” and has no formal solution and to standardize these components. - 2) To minimize the overhead in testing out new ideas and providing solutions which can be provided early while the formal systems are designed. They are much better than the one-of-a-kind PCBs that we have had in the past (and still do in some places ___shhhh.). They are much better than the one-of-a-kind PCBs that we have had in the past (and still do in some places ___shhhh.). In certain applications like the DLPC, they are now a permanent part of the FEL control system. In certain applications like the DLPC, they are now a permanent part of the FEL control system.

Operated by the Southeastern Universities Research Association for the U.S. Dept. Of Energy Thomas Jefferson National Accelerator Facility FEL I would like to thank and acknowledge the following people and organizations for their specific contributions to this work: I would like to thank and acknowledge the following people and organizations for their specific contributions to this work: Al Grippo – for his part in developing the EPICS applications Al Grippo – for his part in developing the EPICS applications Kevin Jordan – for his approval and guidance Kevin Jordan – for his approval and guidance My partners in the FEL I&C group and the entire FEL Team My partners in the FEL I&C group and the entire FEL Team DOE, ONR, JTO & the AFRL for their continuing investment in the Free Electron Laser Project at Jefferson Lab DOE, ONR, JTO & the AFRL for their continuing investment in the Free Electron Laser Project at Jefferson Lab and ‘you’ who have provided me this opportunity to present this work at the 10 th ICALEPCS thank you and ‘you’ who have provided me this opportunity to present this work at the 10 th ICALEPCS thank you Acknowledgments and Thanks... Acknowledgments and Thanks...