03/31/031 ECE 551: Digital System Design & Synthesis Lecture Set 8 8.1: Miscellaneous Synthesis (In separate file) 8.2: Sequential Synthesis

03/30/032 ECE Digital System Design & Synthesis Lecture Synthesis of Sequential Logic Overview  Latches  Edge-triggered flip-flops  Finite state machines (FSMs)  Resets  Gated Clocks

03/30/033 Synthesis of Latches  Implication of latches  Implementation of latches  Implementation issue

03/30/034 Implication of Latches  Latches are synthesized in response to the following:  A variable with an unassigned value on a thread (e. g., missing branches in case or if)  Assignment of value to self (e. g. Q = Q) with either fully or partially assigned threads.  Conditional assignment statement ( ? :) with feedback (equivalent to assignment of value to self).

03/30/035 Implementation of Latches  Forms of storage  Combinational logic with feedback  Multiplexer with feedback  Latch component  Which of the above is the best?

03/30/036 Implementation Issue  Latches (as any storage element) are at the fundamental level asynchronous circuits  Thus, they suffer from asynchronous circuit problems  Example: Multiplexer-based latch:  Q = E D + ~E Q.  Note the feedback

03/30/037 Implementation Issue - 1  Consider this circuit open-loop:  P = E D + ~E Q.  In the face of different path delays as E changes from 1 to 0 with D and Q = 1, the RHS can exhibit a static 1 hazard (will drop momentarily from 1 to 0 in response to the change in E and then return to 1.  But in the closed loop case with Q on the LHS propagating the 0 to the Q on the RHS, the resulting stored value may erroneously become 0!

03/30/038 Implementation Issue - 2  The solution is to add a static hazard elimination term  P = E D + ~E Q + D Q  This term will be present or the problem handled otherwise in a latch component  But what will happen in synthesis?  Conclusion: For a given synthesis tool, it is best to use constructs that will synthesize to a latch, not a multiplexer with feedback or combinational logic

03/30/039 Synthesis of Flip-Flops  Implication of flip-flops  Implementation of flip-flops

03/30/0310 Implication of Flip-flops - 1  Flip-flops are synthesized in response to the following:  A variable that is referenced outside of the scope of the behavior  A variable that is referenced within a behavior before being assigned (including assignment of value to self)  A variable with an unassigned value on a thread (e. g., missing branches in case or if)  The 3 rd condition is the same as one that implies a latch, but the first two are new  What is different here?

03/30/0311 Implication of Flip-flops - 2  Using edge-triggering: (posedge clk) begin A <= B; B <= A; end  Edge sensitivity permits fully assigned threads without unassigned values that are meaningful.  Example 1: Referenced before being assigned

03/30/0312 Implication of Flip-flops - 3  Using edge-triggering: (posedge clk) begin A <= B; end (posedge clk) begin B <= A; end  Example 2: Referenced outside scope of behavior

03/30/0313 Implication of Flip-Flops - 4  If actions, other than synchronous, described with the flip-flop implied by a unassigned value on a thread, the last branch must describe the synchronous activity.  The synchronizing signal is not tested explicitly in the body of the if statement.  Use of if (reset), else if (clk) may not synthesize!

03/30/0314 Comments on Finite State Machines (FSMs) - 1  default: applies only to expression items, not to embedded if, case, or “? :”  Thus, embedded structures must avoid latch formation independently  Pre-assignment before case statement provides default for all  If don’t cares desired need to reinsert using default in case

03/30/0315 Comments on Finite State Machines (FSMs)  State Encoding  Typical assignments Binary count Random Gray - low power One hot - no decoding - fast - low power? Johnson (twisted ring counter) minimal decoding with glitch suppression. Algorithmic - uses state assignment algorithm to achieve specific tradeoffs

03/30/0316 Pragmatics: Resets - 1  assign … deassign allow a separate behavior for an asynchronous reset/set  Simulation efficient, but not universally supported  If library components selected by synthesis tool have sets/resets that do not appear in the Verilog, will be tied to power and ground.

03/30/0317 Pragmatics: Resets - 2  Be sure to a reset on all storage elements where needed.  Asynchronous Power-up Explicit  Synchronous clocked reset Resetting for normal synchronous functionality

03/30/0318 Pragmatics: Gated Clocks  Use only if necessary  Low-power is a use  Often done more globally  The author’s gated clock is NOT a gated clock+  Is a clock enable  and does not achieve the full power savings of a gated clock!  Clock gating details (done in class)  Correct implementations  Dealing with delay