 Program Abstractions  Concepts  ACE Structure

 ACE  Microblock

 Intel uses the term Active Computing Element (ACE) to denote programming abstraction.  It is characterized by  Used to construct packet processing system  Runs on microengines or host  Handle data processing path  Coordinates and synchronizes with other ACE’s  Can have multiple outputs  Can serve as part of pipe lining

 Terminologies  Library ACE – An ACE that has been built by Intel and made available as a part of Intel SDK.  Conventional ACE – An ACE that is built by Intel customers.  MicroACE – An ACE that is made of two components: Core and Microblock. Source Micro- block Transfom Micro- block Sink Micro- block

 There are four conceptual parts  Initialization - It is invoked once, before any other code is executed to built data structure and initialize variable.  Classification - When packet arrives, the ACE classifies the packet.  Actions - An action is invoked whenever a packet satisfies the corresponding classification.  Message and Event management – It generates or handles message and events that provide communication with another ACE or with the underlying hardware.

 Output Targets  Output can be change after it has been compiled.  A programmer create a set of target names and uses a name to specify each output.  During integration process target names can be bound to specific destination.

 ACE Interconnection instead of building a single monotonic ACE software can be divided into several smaller ACEs. Ingress ACE Process ACE Egress ACE Input ports Output ports

 MicroACE  Codes in the ACE run on the StrongARM or on one of the microengines.  Intel provides a mechanism that allows the two components to pass packets in either direction between them. Example : A system that perform IP forwarding with four conceptual ACEs – ingress, egress, IP forwarding and interface to local IP protocol stack.

Core and Microblocks component Stack ACE Ingress ACE (core) Egress ACE (MB) IP ACE (MB) Ingress ACE (MB) Egress ACE (core) IP ACE (core) Strong ARM Microengine I/po/p

 Microblock Groups. microbloack group is Set of microblocks that run on a single microengine. Stack ACE Ingress ACE (core) Egress ACE (MB) IP ACE (MB) Ingress ACE (MB) Egress ACE (core) IP ACE (core) I/po/p Microengine 1Microengine 2

 Replicated Microblocks parallelism can be increases by replicating a microblock group onto multiple microengines.  Dispatch Loop- a machenism to control packet flow among microblocks. Here dispatch loop refer to a small piece of code that control packet flow

Parameter  A buffer handle for a frame that contail a packet  A set of register to store contain information about frame  A variable in which to store a return code

 Exceptions Exception refer to packet passed from a microblock component to corresponding core component on the StrongARM.  ACEs include a queue management named as communication queue to transfer packets between ACEs.  A non-packet communication can be perform by crosscall, the mechanism is related to RPC.  Crosscall are of 3 types Deferred, oneway and twoway.

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