Solid-State Devices & Circuits ECE 342 Solid-State Devices & Circuits 3. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu

Complementary MOS Combine nMOS and pMOS transistors CMOS Characteristics Combine nMOS and pMOS transistors pMOS size is larger for electrical symmetry

CMOS Advantages Virtually, no DC power consumed No DC path between power and ground Excellent noise margins (VOL=0, VOH=VDD) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pMOS size larger to achieve electrical symmetry Latch up

MOSFET Switch MOS approximates switch better than BJT in off state NMOS PMOS Characteristics of MOS Switch MOS approximates switch better than BJT in off state Resistance in on state can vary from 100 W to 1 kW

CMOS Switch CMOS switch is called an inverter

CMOS Switch – Off State nMOS transistor is off OFF State (Vin: low) nMOS transistor is off Path from Vout to V1 is through PMOS Vout: high

CMOS Switch – On State pMOS transistor is off ON State (Vin: high) pMOS transistor is off Path from Vout to ground is through nMOS Vout: low

CMOS Inverter Short switching transient current  low power

Digital Circuits VIH: Input voltage at high state  VIHmin VIL: Input voltage at low state  VILmax VOH: Output voltage at high state  VOHmin VOL: Output voltage at low state  VOLmin Likewise for current we can define Currents into input Currents into output IIH  IIHmax IIL  IILmax IOH  IOHmax IOL  IOLmax

Voltage Transfer Characteristics (VTC) The static operation of a logic circuit is determined by its VTC In low state: noise margin is NML In high state: noise margin is NMH NML NMH VIL and VIH are the points where the slope of the VTC=-1 An ideal VTC will maximize noise margins Optimum:

Switching Time & Propagation Delay input output

Switching Time & Propagation Delay tr=rise time (from 10% to 90%) tf=fall time (from 90% to 10%) tpLH=low-to-high propagation delay tpHL=high-to-low propagation delay Inverter propagation delay:

VTC and Noise Margins For a logic-circuit family employing a 3-V supply, suggest an ideal set of values for Vth, VIL, VIH, VOH, NML, NMH. Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply? Ideal 3V logic implies:

VTC and Noise Margins The gain in the transition region is: Inverting transfer characteristics The gain in the transition region is:

CMOS Noise Margins When inverter threshold is at VDD/2, the noise margin NMH and NML are equalized NMH: noise margin for high input NML: noise margin for low input Vth: threshold voltage Noise margins are typically around 0.4 VDD; close to half power-supply voltage  CMOS ideal from noise-immunity standpoint

Switching Circuit

Nonideal Switch

IV Characteristics of Switches Non-ideal switch Ideal switch

Complementary Switches

Problem A switch has an open (off) resistance of 10MW and close (on) resistance of 100 W. Calculate the two voltage levels of Vout for the circuit shown. Assume RL=5 kW

Problem State 1: S1 off, S2 on RS1=10 MW, RS2=100 W If two switches are used as shown, calculate the two output voltage levels. Assume switches are complementary State 1: S1 off, S2 on RS1=10 MW, RS2=100 W State 2: S1 on, S2 off RS1=100 W, RS2=10 MW

MOSFET Switch MOS approximates switch better than BJT in off state NMOS PMOS Characteristics of MOS Switch MOS approximates switch better than BJT in off state Resistance in on state can vary from 100 W to 1 kW

NMOS Switch

CMOS switch is called an inverter The body of each device is connected to its source  NO BODY EFFECT

CMOS Switch – Off State nMOS transistor is off OFF State (Vin: low) nMOS transistor is off Path from Vout to V1 is through PMOS Vout: high

CMOS Switch – Input Low

CMOS Switch – Input Low NMOS rdsn high PMOS rdsp is low

CMOS Switch – On State pMOS transistor is off ON State (Vin: high) pMOS transistor is off Path from Vout to ground is through nMOS Vout: low

CMOS Switch – Input High

CMOS Switch – Input High NMOS rdsn is low PMOS rdsp high

CMOS Inverter Short switching transient current  low power

CMOS Inverter Advantages of CMOS inverter Output voltage levels are 0 and VDDsignal swing is maximum possible Static power dissipation is zero Low resistance paths to VDD and ground when needed High output driving capability increased speed Input resistance is infinite high fan-out Load driving capability of CMOS is high. Transistors can sink or source large load currents that can be used to charge and discharge load capacitances.

CMOS Inverter VTC QP and QN are matched sedr42021_0456.jpg

CMOS Inverter VTC Derivation Assume that transistors are matched Vertical segment of VTC is when both QN and QP are saturated No channel length modulation effect  l = 0 Vertical segment occurs at vi=VDD/2 VIL: maximum permitted logic-0 level of input (slope=-1) VIH: minimum permitted logic-1 level of input (slope=-1) To determine VIH, assume QN in triode region and QP in saturation region Next, we differentiate both sides relative to vi

CMOS Inverter VTC Substitute vi=VIH and dvo/dvi = -1 After substitutions, we get Same analysis can be repeated for VIL to get

CMOS Inverter Noise Margins Symmetry in VTC  equal noise margins

Matched CMOS Inverter VTC CMOS inverter can be made to switch at specific threshold voltage by appropriately sizing the transistors Symmetrical transfer characteristics is obtained via matching  equal current driving capabilities in both directions (pull-up and pull-down)

VTC and Noise Margins - Problem An inverter is designed with equal-sized NMOS and PMOS transistors and fabricated in a 0.8-micron CMOS technology for which kn’ = 120 mA/V2, kp’ = 60 mA/V2, Vtn =|Vtp|=0.7 V, VDD = 3V, Ln=Lp = 0.8 mm, Wn = Wp = 1.2 mm, find VIL, VIH and the noise margins. Equal sizes NMOS and PMOS, but kn’=2kp’ Vt = 0.7V For VIH: QN in triode and QP in saturation

VTC and Noise Margins – Problem (cont’) (1) Differentiating both sides relative to VI results in: Substitute the values together with:

VTC and Noise Margins – Problem (cont’) (2) (3)

VTC and Noise Margins – Problem (cont’) For VIL: QN is in saturation and QP in triode (1)

VTC and Noise Margins – Problem (cont’)

VTC and Noise Margins – Problem (cont’) Since QN and QP are not matched, the VTC is not symmetric

CMOS Dynamic Operation Exact analysis is too tedious Replace all the capacitances in the circuit by a single equivalent capacitance C connected between the output node of the inverter and ground Analyze capacitively loaded inverter to determine propagation delay

CMOS – Dynamic Operation sedr42021_1006.jpg

CMOS – Dynamic Operation sedr42021_0457a.jpg

CMOS Dynamic Operation Need interval tPHL during which vo reduces from VDD to VDD/2 Which gives Iav is given by

CMOS Dynamic Operation where and this gives

CMOS Dynamic Operation Where an is given by Likewise, tPLH is given by with

CMOS Dynamic Operation and tp is given by Components can be equalized by matching transistors tP is proportional to C reduce capacitance Larger VDD means lower tp Conflicting requirements exist

CMOS – Propagation Delay sedr42021_1007a.jpg

CMOS – Propagation Delay Capacitance C is the sum of: Internal capacitances of QN and QP Interconnect wire capacitance Input of the other logic gate To lower propagation delay Minimize C Increase process transconductance k’ Increase W/L Increase VDD

CMOS Inverter Problem A CMOS inverter for which kn=10 kp=100 mA/V2 and Vt =0.5 V is connected as shown to a sinusoidal signal source having a Thevenin equivalent voltage of 0.1-V peak amplitude and resistance of 100 kW. What signal voltage appears at node A with vI = +1.5 V and vI = -1.5 V?

CMOS Inverter Problem (cont’) For vI = 1.5 V, the NMOS operates in the triode region while the PMOS is off. sedr42021_p1014.jpg

CMOS Inverter Problem (cont’) For vI = -1.5 V, the PMOS operates with sedr42021_p1014.jpg

Propagation Delay - Example Find the propagation delay for a minimum-size inverter for which kn’=3kp’=180 mA/V2 and (W/L)n = (W/L)p=0.75 mm/0.5 mm, VDD = 3.3 V, Vtn = -Vtp = 0.7 V, and the capacitance is roughly 2fF/mm of device width plus 1 fF/device. What does tp become if the design is changed to a matched one? Use the method of average current. Solution 13.38

Propagation Delay - Example

Propagation Delay - Example If both devices are matched, then and

CMOS – Dynamic Power Dissipation In every cycle QN dissipate ½ CVDD2 of energy QP dissipate ½ CVDD2 of energy Total energy dissipation is CVDD2 sedr42021_0458.jpg If inverter is switched at f cycles per second, dynamic power dissipation is:

Power Dissipation - Example In this problem, we estimate the inverter power dissipation resulting from the current pulse that flows in QN and QP when the input pulse has finite rise and fall times. Let Vtn=-Vtp=0.5 V, VDD = 1.8V, and kn=kp=450mA/V2. Let the input rising and falling edges be linear ramps with the 0-to-VDD and VDD-to-0 transitions taking 1 ns each. Find Ipeak. 13.44

Power Dissipation - Example To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from Vt to VDD-Vt, and the height equal to Ipeak. Also, determine the power dissipation that results when the inverter is switched at 100 MHz.

Power Dissipation - Example

Power Dissipation - Example The time when the input reaches Vt is: The time when the input reaches VDD - Vt is: The base of the triangle is

Power Dissipation - Example