Basic I/O Interface Fixed Address Variable Address I/O Instructions: Instructions that transfer data b/w an I/O device(s) and the µP’s accumulator (AL or AX) are called IN and OUT. I/O address is often called port number or port. Fixed Address Variable Address Stored with instruction in ROM (immediate address) Stores in DX register (indirect address) 8-bit address (p8) 16-bit address (p16) A15-A8 (00000000) 2 A7-A0 (address) A15-A0 (DX contains the address) 00H-FFH (0-255) 0000H-FFFFH (0-66535) Opcode Destination, Source IN AL, p8 IN AX, p8 OUT p8, AL OUT p8, AX IN AL, DX IN AX, DX OUT DX, AL OUT DX, AX

Isolated I/O-Mapped I/O Methods of Interfacing I/O devices: Two methods of interfacing I/O(s) with µP. Isolated I/O-Mapped I/O Memory-Mapped I/O Mostly used in Intel’s Hierarchy Used in AVR based Systems (Mostly all types of µC) IN and OUT instructions are used to transfer data b/w µP and I/O(s) MOV instruction is used to transfer data b/w µP and I/O(s) Isolated means isolated address space for memory and I/O I/O device has location(s) (address) on the Memory Map Need separate signals IORC and IOWC generated from RD, WR and IO/M No Need of separate signals like IORC and IOWC p8 are used to access devices like timer, keyboard p16 are used to access devices like serial, parallel ports as well as video and disk drive systems Examples are given above MOV AL, [0356] MOV [0356], AL

Memory-Mapped I/O Isolated-Mapped I/O Separation of Control Signals I/O Map of a Personal Computer

Basic Input and Output Interface: Basic input device is a set of three-state buffers Basic output device is a set of data latches Data Bus After OUT instruction execution, Data presents only for 1.0 µs. Without Latch, viewer can never See the LED illumination Decoding Circuitry Decoding Circuitry

Handshaking: I/O devices accept or release information at much slower rate then µP Handshaking method, synchronizes the I/O(s) with µP. Ex: Parallel Printers Notes About Interfacing Circuitry: Input TTL Logic 0 = 0.0v-0.8v Input TTL Logic 1 = 2.0v-5.0v Output TTL Logic 0 = 0.0v-0.4v Output TTL Logic 1 = 2.4v-5.0v Logic 0 = 0.0-2.0mA Logic 1 = 0.0-400µA

I/O Port Address Decoding: I/O address decoding is very similar to memory address decoding Difference => Memory address decoding (A19-A0) => Isolated I/O address decoding (A15-A0) Control Signals OCTAL BUFFER 74LS244

Input Address Decoding: Design for “ IN AL, 9FH” Design for “ IN AL, 5FH”

--VHDL code for the decoder of fig 11-11 library ieee; use ieee.std_logic_1164.all; entity DECODER_11_11 is port ( A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC ); end; architecture V1 of DECODER_11_11 is Begin D0 <= not ( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and not A0); D1 <= not ( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and A0); D2 <= not ( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and not A0); D3 <= not ( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and A0); D4 <= not ( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and not A0); D5 <= not ( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and A0); D6 <= not ( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and not A0); D7 <= not ( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and A0); end V1;

Output Address Decoding: Design for “ OUT 99H, AL” Design for “ OUT 31FH,AL”

Decoding 16-bit I/O port Addressing: --VHDL code for the decoder of fig 11-11 library ieee; use ieee.std_logic_1164.all; entity DECODER_11_11 is port ( Z, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC ); end; architecture V1 of DECODER_11_11 is Begin D0 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and not A0); D1 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and A0); D2 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and not A0); D3 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and A0); D4 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and not A0); D5 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and A0); D6 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and A2 and A1 and not A0); D7 <= not ( not Z and A7 and A6 and A5 and A4 and not A3 and A2 and A1 and A0); end V1; Z

16-bit Wide I/O Ports: 8086, 80186, 80286, 80386 has 16-bit wide data bus. So Two separate banks or sections are needed for sending or receiving information (data).

8-bit Output Devices Located at 40H and 41H: --VHDL code for the decoder of fig 11-14 library ieee; use ieee.std_logic_1164.all; entity DECODER_11_14 is port ( BHE, IOWC, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC; CLK1, CLK2: out STD_LOGIC ); end; architecture V1 of DECODER_11_14 is Begin CLK1 <= BHE or IOWC or A7 or not A6 or A5 or A4 or A3 or A2 or A1 or A0; CLK2 <= BHE or IOWC or A7 or not A6 or A5 or A4 or A3 or A2 or A1 or not A0; end V1; CLK1 CLK2

8-bit Input Devices Located at 64H and 65H : --VHDL code for the decoder of fig 11-15 library ieee; use ieee.std_logic_1164.all; entity DECODER_11_15 is port ( IORC, A7, A6, A5, A4, A3, A2, A1: in STD_LOGIC; O0: out STD_LOGIC ); end; architecture V1 of DECODER_11_15 is Begin O0 <= IORC or A7 or not A6 or not A5 or A4 or A3 or not A2 or A1; end V1;

PROGRAMMABLE PERIPHERAL INTERFACE (82C55): 40-pin DIP chip Separately accessible ports A, B and C Each PORT can be programmed as INPUT or OUTPUT Basic Pin Description of 82C55: PORTA (PA0-PA7): 8-bit port A programmed all as input or all as output PORTB (PB0-PB7): 8-bit port B programmed all as input or all as output PORTC (PC0-PC7): 8-bit port C programmed all as input or all as output It can also be split into two parts CU (Upper Bits PC4-PC7) and CL (Lower Bits PC0-PC3). Each can be used for INPUT or OUTPUT Any of PC0 to PC7 can be programmed individually

RD and RW: Two active low input signals to 82C55 Isolated-Mapped I/O: 1- IORC and 2- IOWC Memory-Mapped I/O: 1- MEMR and 2- MEMW RESET: Active high input signal clear the command (control) register A0, A1and CS: CS (Chip Select) selects the entire chip. Pins A0 and A1 are used to access ports A, B, C and command register

Command Word Format (I/O MODE): Before using PORTs, command register must be programmed. Command register can be programmed in two ways, each called Command Byte A (when register’s MSB Bit-7 = 1) Command Byte B (when register’s MSB Bit-7 = 0) MODE 0: Used for basic I/O operation MODE 1: Used as PORTX and handshaking signals PCX-PCX MODE 2: Used for bi-directional operation of PORTA

MODE-0 OPERATION: Mode-0 causes the 82C55 to function as either a buffered input device or a latched output device

I/O PORT NUMBERS 0700H-0703H --VHDL code for the decoder of fig 11-18 library ieee; use ieee.std_logic_1164.all; entity DECODER_11_21 is port ( IOM, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2: in STD_LOGIC; D0: out STD_LOGIC ); end; architecture V1 of DECODER_11_17 is Begin D0 <= not IOM or A15 or A14 or A13 or A12 or A11 or not A10 or not A9 or not A8 or A7 or not A6 or A5 or A4 or A3 or A2; end V1;

;write here 7-Segement display pattern ;for each .CODE .DATA MEM-1 DB _,_,_,_,_,_,_,_ ;write here 7-Segement display pattern ;for each .CODE MOV AL, 10000000B MOV DX,703H OUT DX, AL CALL DISP .EXIT END DELAY PROC NEAR USES CX MOV CX, XXXX D1: LOOP D1 RET DELAY ENDP