1. Khaled A. Al-Utaibi alutaibi@uoh.edu.sa

2.  I/O Ports  I/O Space VS Memory Space  80x86 I/O Instructions − Direct I/O Instructions − Indirect I/O Instructions − String I/O Instructions  Accessing I/O Ports in 80x86 Processors  Designing a Parallel Input Port  Designing a Parallel Output Port

3.  Processors use I/O devices to input, process, and then output information to perform useful work.  The I/O devices can be connected to a computer system through I/O ports.  An I/O port is similar to a memory location in that each port must have its own address.  With the 80x86 processors, the port address is 16 bits long, allowing addresses in the range 0000 through FFFFH.  The ports themselves may be 8, 16, or 32 bits wide. The resulting interface is therefore said to be using parallel I/O.

4.  The 80x86 processors use the M/IO signal to separate I/O space from memory space (as shown in the next figure).  When this signal is high, addresses output by the processor will be interpreted as memory locations.  However, when this line is low, those same addresses will be interpreted as I/O locations.  Because I/O addresses are restricted to 16 bits, valid I/O addresses range from 0000 to FFFFH.

6.  The 80x86 processors have just two basic I/O instruction IN and OUT.  However, there are several variations of each, depending on: − the size of the data to be input or output (byte, word, or double-word), − the method of specifying the port (direct or indirect), and − the method of specifying the source and destination of the data.  These are summarized in the next table.

8.  The direct I/O instructions supply the port address (which must be a number between 0 and FFH) as part of the instruction. For example: IN AL, 27H ; input the byte at port 27H ; to register AL  Note that all data must flow through the accumulator register (AL, AX, EAX).  Thus, to output the 16-bit quantity in register BX to port 27H, two instructions are required: MOV AX,BX ; move data to AX OUT 26H, AX ; output the AX to port 26H  In this last instruction, AL is output to port 26H and AH to port 27H.

9.  To access the full range of I/O ports from 0 to FFFFH, the indirect I/O instructions must be used.  For these instructions, register DX must be preloaded with the port address.  For example, to input the 32-bit quantity at port 1000H, use the instructions: MOV DX,1000H ; load port address into DX IN EAX,DX ; input the word whose port ; address is in DX to EAX  Because four bytes of data are being input, ports 1000, 1001, 1002, and 1003 will all be accessed for this last instruction.

10.  The direct and indirect I/O instructions require that all data pass through the accumulator.  The string I/O instructions allow data to pass directly to or from a memory location.  For example, assume 4K of data (in a segment named D_DATA with the first byte at an offset called TOP) is to be output to a disk drive at port 47H.

11.  The following instructions can be used. MOV AX,D_DATA ; get segment address MOV DS,AX ; and copy to DS LEA SI,TOP ; offset address of the data to SI CLD ; clear direction flag (auto-incr) MOV DX,47H ; DX points to the I/O port MOV CX,1000H ; CX is the byte counter (4K) REP OUTSB ; Output the contents of the data ; table to the I/O port  In this example, the REP OUTSB instruction outputs a byte from memory pointed to by DS:SI, increments SI to point to the next memory location, and decrements the byte counter in CX.  The instruction is repeated until CX equals zero.

12.  The 8086 processor has a 16-bit data bus.  It uses the A0 address line and the BHE (bus high enable) signal to identify which data lines will be involved in the data transfer.  When A0 only is low, data is transferred on D0- D7.  When BHE' only is low, data is transferred on D8- D15.  When A0 and BHE' are both low, data is transferred on all 16 data lines.  These cases are shown in the next table.

14.  When the 8086 executes the instruction IN AL,0, it places the 16-bit I/O address 0000 0000 0000 0000 on bus lines A15 through A0 and makes BHE’ signal high  The instruction IN AL,1 outputs the 16-bit I/O address 0000 0000 0000 0001, and makes BHE' signal low.  The instruction IN AX, 0 outputs the 16-bit I/O address 0000 0000 0000 0000, and makes the BHE’ signal low.  This instruction results in a 16-bit word access (D0-D15).

16.  The 386 & 486 processors have 32-bit data bus and can access four bytes of memory (or four consecutive I/O Ports) in one bus cycle.  The A0 & A1 address lines, which would identify bytes within this four-byte boundary, are not present.  Instead four active-low byte enable signals (BE3'- BE0') are provided.  The next table show which set of data bus lines will be active for each byte enable.

18.  When the 386 or 486 executes the instruction IN AL,0, it places the 14-bit I/O address 0000 0000 0000 00-- on bus lines A15 through A2.  It also activates the BE0' byte enable.  Similarly, the instruction IN AL,1 outputs the same 14-bit I/O address, but this time BE1' is made active.  A 16-bit word access causes two byte enables to be active simultaneously.  For example, when the instruction IN AX,0 is executed, the same 14-bit I/O address is output, but this time BE0' and BE1' are made active.  BE2' and BE3' would be active for the instruction IN AX,2.  All four ports can be accessed at once with the instruction IN EAX,0. In this case, all of the byte enables are made active.

20.  The Pentium processors are similar to the 386 and 486 processors but access eight bytes at a time.  For these processors, the A0-A2 address lines are not needed.  Eight byte enable signals are provided (BE7'- BE0').

21.  Example 1: Design a simple 8-bit input interface using 8- switches and 8 tri-state buffers.

22.  Example 2: Show how to design a 16-bit input port for the 8086 processor using the 8-switches input interface designed in Example 1. Assume your design will be mapped to port number 6. Step (1): Design the address decoding A 15 -A 12 A 11 -A 8 A 7 -A 4 A 3 A 2 A 1 A 0 0000 0000 0000 0 1 1 0 (Even Byte) 0000 0000 0000 0 1 1 1 (Odd Byte) Address Decoding Chip Select (CS’) Step (2): Design the Read Logic RD’ = IOR’

24.  Example 3: Design a simple 8-bit Output interface using 8- LEDs and 8 latches (74373).

25.  Example 4: Show how to design a 16-bit output port for the 8086 processor using the 8-LEDs output interface designed in Example 3. Assume your design will be mapped to port number 4. Step (1): Design the address decoding A 15 -A 12 A 11 -A 8 A 7 -A 4 A 3 A 2 A 1 A 0 0000 0000 0000 0 1 0 0 (Even Byte) 0000 0000 0000 0 1 0 1 (Odd Byte) Address Decoding Chip Select (CS’) Step (2): Design the Read Logic WR’ = IOW’