VHDL Hardware Description Language

GUIDELINES How to write HDL code: How to write HDL code:

GUIDELINES How NOT to write HDL code: How NOT to write HDL code:

Think Hardware NOT Software Poorly written VHDL code will either be: Poorly written VHDL code will either be: –Unsynthesizable –Functionally incorrect –Lead to poor performance/area/power results

VHDL code basic structure Entity Entity (I/O and generic declaration) Architecture Architecture structural (structure description) rtl (register transfer level description) behavioral (high-level description)

Entity declaration ENTITY entity_name IS PORT (port_name_1 : port_type_1; port_name_2: port _type_2; port_name_2: port _type_2; port_name_n: port_type_n); port_name_n: port_type_n); END entity_name; END entity_name;

Port types PORT DIRECTION PORT DIRECTION - IN -OUT-INOUT SIGNAL TYPE SIGNAL TYPE –BIT –BIT_VECTOR(WIDTH -1 DOWNTO 0) –STD_LOGIC –STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0)

Entity declaration example (1/2) ENTITY and_gate IS PORT (i1: IN BIT; i2: IN BIT; i2: IN BIT; O: OUT BIT); O: OUT BIT); END and_gate;

Entity declaration example (2/2) Library ieee; Use ieee.std_logic_1164.all; ENTITY adder IS PORT (i1: IN STD_LOGIC_VECTOR(3 DOWNTO 0); i2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); i2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); carry: OUT STD_LOGIC); carry: OUT STD_LOGIC); END adder;

Example

Architecture declaration ARCHITECTURE architecture_name OF entity_name IS component declaration; component declaration; signal declaration; signal declaration; BEGIN BEGIN component instantiation component instantiation sequential statements (processes) sequential statements (processes) concurrent statements concurrent statements END [architecture_name]; END [architecture_name];

Component declaration COMPONENT component_name PORT (port_name_1 : port_type_1; PORT (port_name_1 : port_type_1; port_name_2: port _type_2; port_name_2: port _type_2; port_name_n: port_type_n); port_name_n: port_type_n); END COMPONENT; END COMPONENT;

Component declaration example COMPONENT and_gate PORT (i1: IN BIT; i2: IN BIT; i2: IN BIT; O: OUT BIT); O: OUT BIT); END COMPONENT;

Signal declaration SIGNAL signal_name : signal_type; Examples SIGNAL data_bus: std_logic_vector(7 downto 0); SIGNAL clock: std_logic; SIGNAL count : bit_vector(5 downto 0);

Component instantiation (nominal) Label: component_name PORT MAP( port_name1 => signal_name1, PORT MAP( port_name1 => signal_name1, port_name2 => signal_name2, port_name2 => signal_name2, … port_nameN => signal_nameN); port_nameN => signal_nameN);

Example U_adder: adder PORT MAP(i1 => add1, i2 => add2, i2 => add2, sum => s, sum => s, carry => c); carry => c);

Component instantiation (positional) Label: component_name PORT MAP( signal_name1, PORT MAP( signal_name1, signal_name2, signal_name2, … signal_nameN); signal_nameN);

Example U_adder: adder PORT MAP(add1, add2, add2, s, s, c); c);

Structural description example (1/2) ENTITY gates IS PORT (i0,i1,i2,i3: std_logic; o: out std_logic); END gates; ARCHITECTURE str of gates IS COMPONENT and_gate PORT (i1,i2: in std_logic; o: out std_logic); END COMPONENT; SIGNAL s1,s2: std_logic; BEGIN

Structural description example (2/2) U_and1: and_gate PORT MAP(i1 => i0, i2 => i1, o => s1); U_and2: and_gate PORT MAP(i1 => i2, i2 => i3, o => s2); U_and3: and_gate PORT MAP(i1 => s1, i2 => s2, o => o); END;

VHDL operators Arithmetic Arithmetic +, -, *, Synthesizable /, abs, rem, mod, **Non-synthesizable Logical Logical AND, OR, NOT, NAND, NOR, XOR, XNOR Relational Relational =, /=,, =

Signal assignment signal_name <= signal_value; Examples signal a: std_logic; signal b: std_logic_vector(6 downto 0); signal c: std_logic_vector(3 downto 0); signal d: std_logic_vector(2 downto 0); CorrectIncorrect a <= ‘1’;a <= “01”; b <= “ ”;b <= ‘0’; b(1) <= ‘0’; c ‘0’);c ‘0’);c <= ‘0000’; d ‘0’, others => ’1’);d ‘0’, others => ’1’);d <= b & c; b <= c & d;b(3 downto 1) <= d(1 downto 0); b(5 downto 3) <= d;

The “after” clause Used to assign signals with delay, modeling circuit behaviour a <= d after 5 ns;-- 5 ns wire delay a <= d after 5 ns;-- 5 ns wire delay b <= a and c after 20 ns;-- 20 ns gate delay b <= a and c after 20 ns;-- 20 ns gate delay Not synthesizable, is ignored by synthesis tools Useful in testbenches for creating input signal waveforms clk <= not clk after 20 ns; ns clock period clk <= not clk after 20 ns; ns clock period rst_n <= ‘0’, rst_n <= ‘0’, ‘1’ after 210 ns;

Concurrent statements – delta time b <= not a;(a = ‘1’, b = ‘1’, c= ‘0’) c <= a xor b; Timeabc b <= not a;(a = ‘1’, b = ‘1’, c= ‘0’) c <= a xor b; Timeabc δ100 δ100 2δ10 1 b <= not a;(a = ‘1’, b = ‘1’, c =‘0’) c <= a xor b; Timeabc δ100 δ100

Concurrent statements Multiple driver error Multiple driver error c <= a AND b; …. c <= d OR e;

Combinational circuit description ENTITY gates is port (a: in std_logic; port (a: in std_logic; d: out std_logic); d: out std_logic); end gates; Architecture rtl of gates is signal b: std_logic; begin b <= not a; b <= not a; d <= c xor b; --d<=c xor (not a); d <= c xor b; --d<=c xor (not a); end rtl;

GENERATE STATEMENTS (concurrent only) Used to generate multiple instances of a component in homogeneous architectures Used to generate multiple instances of a component in homogeneous architectures Z_Gen: For i in 0 to 7 generate z(i) <= x(i) AND y(i+8); end generate;

Generate example (1/2) ENTITY cell_array IS PORT (i: in std_logic_vector(63 downto 0); o: out std_logic_vector(63 downto 0) ); END ENTITY cell_array; ARCHITECTURE str OF cell_array IS COMPONENT cell PORT (i_north: in std_logic; i_west: in std_logic; i_east: in std_logic; o_east: out std_logic; o_west: out std_logic; o_south: out std_logic ); end component; signal west: std_logic_vector(62 downto 0); signal east: std_logic_vector(62 downto 0); BEGIN

Generate example (2/2) U_cell_0: cell PORT MAP (i_north => i(0), i_west => '0', i_east => west(0), o_east => east(0), o_west => open, o_south => o(0) ); U_cell_63: cell PORT MAP (i_north => i(63), i_west => east(62), i_east => '0', o_east => open, o_west => west(62), o_south => o(63) ); U_top_gen: for i in 1 to 62 generate U_cell_i: cell PORT MAP (i_north => i(i), i_west => east(i-1), i_east => west(i), o_east => east(i), o_west => west(i-1), o_south => o(i) ); end generate; end;

Generate example 2 (1/5) ENTITY cell_array IS PORT (i: in std_logic_vector(3 downto 0); o: out std_logic_vector(3 downto 0) ); END ENTITY cell_array; -- ARCHITECTURE str OF cell_array IS COMPONENT cell PORT (i_north: in std_logic; i_west: in std_logic; i_east: in std_logic; o_east: out std_logic; o_west: out std_logic; o_south: out std_logic ); end component; type sig_array is array (3 downto 0) of std_logic_vector(3 downto 0); type sig_array2 is array (2 downto 0) of std_logic_vector(3 downto 0); signal south: sig_array2; signal west: sig_array; signal east: sig_array;

Generate example 2 (2/5) BEGIN U_cell_0_0: cell PORT MAP (i_north => i(0), i_west => '0', i_east => west(0)(0), o_east => east(0)(0), o_west => open, o_south => south(0)(0) ); U_cell_0_3: cell PORT MAP (i_north => i(3), i_west => west(0)(3), i_east => '0', o_east => east(0)(3), o_west => west(0)(3), o_south => south(0)(3) ); U_cell_3_0: cell PORT MAP (i_north => north(2)(0), i_west => '0', i_east => west(3)(0), o_east => east(3)(0), o_west => open, o_south => o(0) );

Generate example 2 (3/5) U_cell_3_3: cell PORT MAP (i_north => north(2)(3), i_west => west(3)(3), i_east => '0', o_east => open, o_west => west(3)(3), o_south => o(3) ); U_top_gen: for i in 1 to 2 generate U_cell_i_0: cell PORT MAP (i_north => i(i), i_west => east(i-1)(0), i_east => west(i)(0), o_east => east(i)(0), o_west => west(i-1)(0), o_south => south(i)(0) ); end generate; U_bottom_gen: for i in 1 to 2 generate U_cell_i_3: cell PORT MAP (i_north => south(i)(2), i_west => east(i-1)(3), i_east => west(i)(3), o_east => east(i)(3), o_west => west(i-1)(3), o_south => o(i) ); end generate;

Generate example 2 (4/5) U_left_gen: for i in 1 to 2 generate U_cell_0_i: cell PORT MAP (i_north => south(0)(i), i_west => '0', i_east => west(0)(i), o_east => east(0)(i), o_west => open, o_south => south(0)(i) ); end generate; U_right_gen: for i in 1 to 2 generate U_cell_3_i: cell PORT MAP (i_north => south(2)(i), i_west => east(3)(i-1), i_east => '0', o_east => east(3)(i), o_west => west(3)(i-1), o_south => south(3)(i) ); end generate;

Generate example 2 (5/5) U_inner_gen_x: for i in 1 to 2 generate U_inner_gen_y: for j in 1 to 2 generate U_cell_i_j: cell PORT MAP (i_north => south(i-1)(j), i_west => east(i)(j-1), i_east => west(i)(j), o_east => east(i)(j), o_west => west(i)(j-1), o_south => south(i)(j) ); end generate; END ARCHITECTURE str;

Arithmetic unit description Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; ENTITY add1 is port (a, b: in std_logic; port (a, b: in std_logic; cin: in std_logic; cin: in std_logic; sum: out std_logic; sum: out std_logic; cout: out std_logic); cout: out std_logic); end add1; end add1; ARCHITECTURE rtl of add1 is Signal s: std_logic_vector(1 downto 0); begin s <= (‘0’ & a) + b + cin; s <= (‘0’ & a) + b + cin; sum <= s(0); sum <= s(0); cout <= s(1); cout <= s(1);end;

Example Describe a 5-bit multiplier in VHDL.

When statement (concurrent)– describing MUXs Port/signal <= value1 WHEN condition1 [ELSE value2 when condition2 [ELSE value2 when condition2 …] …] ELSE valueN; ELSE valueN; ENTITY mux IS PORT (i0: in std_logic; PORT (i0: in std_logic; i1: in std_logic; i1: in std_logic; s: in std_logic; s: in std_logic; o: out std_logic); o: out std_logic); END mux; ARCHITECTURE rtl OF mux IS BEGIN o <= i0 when s = ‘0’ else i1; o <= i0 when s = ‘0’ else i1; END RTL;

with statement (concurrent)– describing MUXs WITH signal SELECT port/signal <= expression1 WHEN value1, port/signal <= expression1 WHEN value1, expression2 WHEN value2, expression2 WHEN value2, … expressionN WHEN OTHERS; expressionN WHEN OTHERS; ENTITY mux IS PORT (i0: in std_logic; PORT (i0: in std_logic; i1: in std_logic; i1: in std_logic; s: in std_logic; s: in std_logic; o: out std_logic); o: out std_logic); END mux; ARCHITECTURE rtl OF mux IS BEGIN WITH s SELECT o <= i0 WHEN ‘0’, o <= i0 WHEN ‘0’, i1 WHEN OTHERS; i1 WHEN OTHERS; END rtl;

Sequential statements (1) process [process_name:] PROCESS (sensitivity list) BEGIN BEGIN sequential statements sequential statements END PROCESS [process_name];

COMBINATIONAL PROCESS PROCESS(a, b, c) BEGIN d <= (a AND b) OR c; d <= (a AND b) OR c; END PROCESS; ALL input signals must be in sensitivity list or latches will be produced!

If statement (sequential)– describing MUXs If condition1 then signal1 <= value1; signal1 <= value1; signal2 <= value2; signal2 <= value2; elsif condition2 then signal1 <= value3; signal1 <= value3; signal2 <= value4; signal2 <= value4; … [ELSE [ELSE signal1 <= valuen-1; signal1 <= valuen-1; signal2 <= valuen;] signal2 <= valuen;] end if; ENTITY mux IS PORT (i0: in std_logic; PORT (i0: in std_logic; i1: in std_logic; i1: in std_logic; s: in std_logic; s: in std_logic; o: out std_logic); o: out std_logic); END mux; ARCHITECTURE rtl OF mux IS BEGIN process(i0, i1, s) BEGIN If s = ‘0’ then o <= i0; o <= i0;else o <= i1; o <= i1; end if; end process; END rtl;

CASE statement (sequential)– describing MUXs CASE expression IS when value1 => when value1 => signal1 <= value2; signal1 <= value2; signal2 <= value3; signal2 <= value3; when value4 => when value4 => signal1 <= value4; signal1 <= value4; signal2 <= value5; signal2 <= value5; [when others => [when others => signal1 <= valuen-1; signal1 <= valuen-1; signal2 <= valuen;] signal2 <= valuen;] end CASE; ENTITY mux IS PORT ( i0: in std_logic; PORT ( i0: in std_logic; i1: in std_logic; i1: in std_logic; s: in std_logic; s: in std_logic; o: out std_logic ); o: out std_logic ); END mux; ARCHITECTURE rtl OF mux IS BEGIN process(i0, i1, s) BEGIN CASE s IS WHEN ‘0’ => o <= i0; o <= i0; WHEN OTHERS => s <= i1; s <= i1; end CASE; end process; END rtl;

Example Describe a 3-bit 4-to-1 MUX Describe a 3-bit 4-to-1 MUX

CLOCKED PROCESS (Latch with asynchronous reset) PROCESS(clk, rst_n) BEGIN IF rst_n = ‘0’ THEN IF rst_n = ‘0’ THEN q ‘0’); q ‘0’); ELSIF clk= ‘1’ THEN ELSIF clk= ‘1’ THEN q <= d; q <= d; END IF; END IF; END PROCESS;

CLOCKED PROCESS (Latch with synchronous reset) PROCESS(clk) BEGIN IF clk = ‘1’ THEN IF clk = ‘1’ THEN if rst_n = ‘0’ then if rst_n = ‘0’ then q ‘0’); q ‘0’); else q <= d; else q <= d; end if; end if; END IF; END IF; END PROCESS;

CLOCKED PROCESS (Flip-flop with asynchronous reset) PROCESS(clk, rst_n) BEGIN IF rst_n = ‘0’ THEN IF rst_n = ‘0’ THEN q ‘0’); q ‘0’); ELSIF clk’event and clk= ‘1’ THEN ELSIF clk’event and clk= ‘1’ THEN q <= d; q <= d; END IF; END IF; END PROCESS;

CLOCKED PROCESS (Flip-flop with synchronous reset) PROCESS(clk) BEGIN IF clk’event and clk= ‘1’ THEN IF clk’event and clk= ‘1’ THEN IF rst_n = ‘0’ THEN IF rst_n = ‘0’ THEN q ‘0’); q ‘0’); else q <= d; else q <= d; end if; end if; END IF; END IF; END PROCESS;

for loop statement – shift register [label]: for identifier in range loop statements statements end loop; ENTITY shift_reg is port(clk, rst_n: in std_logic; input: in std_logic; output: out std_logic); end shift_reg; Architecture rtl of shift_reg is signal d: std_logic_vector(3 downto 0); begin process(clk, rst_n) begin if rst_n = ‘0’ then d ‘0’); elsif rising_edge(clk) then d(0) <= input; for i in 0 to 3 loop d(i+1) <= d(i); end loop; end if; end process; output <= d(3); end;

CLOCKED VS COMBINATIONAL PROCESS (1/2) process(a, b, c) BEGIN CASE c IS WHEN ‘0’ => q <= a; q <= a; WHEN OTHERS => q <= b; q <= b; end CASE; end process; process(clk, rst) BEGIN If rst = ‘1’ then q <= ‘0’; q <= ‘0’; elsif clk’event and clk = ‘1’ then CASE c IS WHEN ‘0’ => q <= a; q <= a; WHEN OTHERS => q <= b; q <= b; end CASE; end if; end process;

CLOCKED VS COMBINATIONAL PROCESS (2/2) PROCESS(a, b, c) BEGIN d <= (a AND b) OR c; d <= (a AND b) OR c; END PROCESS; PROCESS(clk, rst) BEGIN if rst = ‘1’ then if rst = ‘1’ then d <= ‘0’; d <= ‘0’; elsif clk’event and clk= ‘1’ then d <= (a AND b) OR c; d <= (a AND b) OR c; end if; END PROCESS;

EXAMPLE: BINARY UPCOUNTER PROCESS(clk)begin if clk’event and clk=‘1’ then if clk’event and clk=‘1’ then if rst_n = ‘0’ then –-synchronous reset if rst_n = ‘0’ then –-synchronous reset count ‘0’); count ‘0’); else else if en = ‘1’ then --count enable if en = ‘1’ then --count enable count <= count + ‘1’; count <= count + ‘1’; end if; end if; end process;

EXAMPLE DESCIBE A BINARY UP/DOWN COUNTER WITH ENABLE THAT COUNTS UPTO 12 AND THEN STARTS AGAIN FROM ZERO DESCIBE A BINARY UP/DOWN COUNTER WITH ENABLE THAT COUNTS UPTO 12 AND THEN STARTS AGAIN FROM ZERO

The integer type Signal signal_name: integer range range_low to range_high Signal signal_name: integer range range_low to range_high Examples: Examples: –Signal count: integer range 0 to bit counter –Signal k: integer range 0 to bit counter

Binary up counter ver2 ARCHITECTURE rtl of counter is signal count: integer range 0 to 31; -- 5-bit counter beginPROCESS(clk) begin begin if clk’event and clk=‘1’ then if clk’event and clk=‘1’ then if rst_n = ‘0’ then –-synchronous reset if rst_n = ‘0’ then –-synchronous reset count <= 0; count <= 0; else else if en = ‘1’ then --count enable if en = ‘1’ then --count enable count <= count + 1; count <= count + 1; end if; end if; end process; end process;end;

TESTBENCH Entity testbench_name is end testbench_name; ARCHITECTURE architecture_name of testbench_name IS COMPONENT declaration Signal declaration --signal clk: std_logic:=‘0’; BEGIN Component instantiation { clk <= not clk after 40 ns; --80 ns clock period a <= ‘1’, a <= ‘1’, ‘0’ after 50 ns, ‘0’ after 50 ns, ‘1’ after 100 ns; } ‘1’ after 100 ns; }end;

TESTBENCH EXAMPLE Entity testbench is Entity testbench is end testbench; end testbench; Architecture test of testbench is Architecture test of testbench is component mux component mux PORT (i0: in std_logic; PORT (i0: in std_logic; i1: in std_logic; i1: in std_logic; s: in std_logic; s: in std_logic; o: out std_logic); o: out std_logic); END component; END component; signal i0, i1, s, o: std_logic; signal i0, i1, s, o: std_logic; begin U_mux: mux port map ( i0 =>i0, i1=>i1, s=>s, o=> o); i0 <= ‘0’, i0 <= ‘0’, ‘1’ after 50 ns, ‘1’ after 50 ns, ‘0’ after 100 ns, ‘0’ after 100 ns, ‘1’ after 150 ns, ‘1’ after 150 ns, ‘0’ after 200 ns, ‘0’ after 200 ns, ‘1’ after 250 ns, ‘1’ after 250 ns, ‘0’ after 300 ns, ‘0’ after 300 ns, ‘1’ after 350 ns; ‘1’ after 350 ns; i1 <= ‘0’, i1 <= ‘0’, ‘1’ after 100 ns, ‘1’ after 100 ns, ‘0’ after 200 ns, ‘0’ after 200 ns, ‘1’ after 300 ns; ‘1’ after 300 ns; s <= ‘0’, s <= ‘0’, ‘1’ after 200 ns; ‘1’ after 200 ns; end test;

FINITE STATE MACHINES

FINITE STATE MACHINE IMPLEMENTATION

Mealy machines (1/3) ENTITY fsm is port(clk, rst_n, a, b: in std_logic; o: out std_logic); END ENTITY fsm; ARCHITECTURE rtl of fsm is Type state is (state0, state1); Signal state_pr, state_nx: state;

Mealy machines (2/4) BEGIN Process(clk, rst_n) --sequential part begin if (rst_n=‘0’) then if (rst_n=‘0’) then state_pr <= state0; --default state state_pr <= state0; --default state elsif rising_edge(clk) then elsif rising_edge(clk) then state_pr <= state_nx; state_pr <= state_nx; end if; end if; end process;

Mealy machines (3/4) process(a, state_pr) --combinational part begin CASE state_pr is CASE state_pr is WHEN state0 => WHEN state0 => if (a = ‘1’) then if (a = ‘1’) then state_nx <= state1; state_nx <= state1; output ; output ; else else state_nx <= state0; --optional state_nx <= state0; --optional output ; output ; end if; end if;

Mealy machines (4/4) WHEN state1 => if (a = ‘1’) then if (a = ‘1’) then state_nx <= state0; state_nx <= state0; output ; --Mealy machine output ; --Mealy machine else else state_nx <= state1; --optional state_nx <= state1; --optional output ; --Mealy machine output ; --Mealy machine end if; end if; end CASE; end process;

Moore machines process(a, state_pr) --combinational part begin CASE state_pr is CASE state_pr is WHEN state0 => WHEN state0 => output ; --Moore machine output ; --Moore machine if (a = ‘1’) then if (a = ‘1’) then state_nx <= state1; state_nx <= state1; else else state_nx <= state0; --optional state_nx <= state0; --optional end if; end if;

MOORE MACHINES WHEN state1 => output ; --Moore machine output ; --Moore machine if (a = ‘1’) then if (a = ‘1’) then state_nx <= state0; state_nx <= state0; else else state_nx <= state1; --optional state_nx <= state1; --optional end if; end if; end CASE; end process;

EXAMPLE: OUT-OF- SEQUENCE COUNTER DESCRIBE A COUNTER WITH THE FOLLOWING SEQUENCE: DESCRIBE A COUNTER WITH THE FOLLOWING SEQUENCE: –“000” => “010” => “011” => “001” => “111” => “000”

Variables variable variable_name: variable_type variable variable_name: variable_type variable_name := variable_value variable_name := variable_value Examples: Examples: –variable x: integer range 0 to 7; –Variable count: std_logic_vector(3 downto 0) –x := 2; –count := “1110”;

Signals vs. variables Signal: Signal: –can be used anywhere –represents circuit interconnect –value is updated at the end of process Variable: Variable: –only in sequential code (process, function, procedure) –Represents local information –value is updated immediately

PACKAGES Used for declaring global constants and functions Used for declaring global constants and functions Package must be declared in the include libraries before the entity declaration Package must be declared in the include libraries before the entity declaration

PACKAGE EXAMPLE PACKAGE tsu_pkg is CONSTANT word_length: integer := 32; --processor word length CONSTANT thid_length: integer := 16; --thread id length CONSTANT cntx_length: integer := 0; --context length CONSTANT nof_ready_count: integer:= 8; --# ready counts TYPE sync_data_type is ARRAY (nof_ready_count downto 0) of std_logic_vector(word_length-1 downto 0); function LOG (X : integer) return integer; --logarithm base 2 end package;

Using a package Package must be declared in the include libraries before the entity declaration Package must be declared in the include libraries before the entity declaration Library work; Use work.tsu_pkg.all; Entity …

Generics An alternative way of declaring parameters, valid only for a single entity. An alternative way of declaring parameters, valid only for a single entity. ENTITY counter is GENERIC (wordlength: integer:= 8); PORT (clk, rst_n, en: in std_logic; count: out std_logic_vector(wordlength-1 downto 0) ); END counter;

FUNCTIONS PACKAGE body tsu_pkg is function LOG (X : integer) return integer is variable i: integer range 0 to pe_num; variable modulus, modulus_copy: integer range 0 to pe_num; variable remainder, remainder_detect: integer range 0 to 1; variable result: integer range 0 to 20:=0; begin modulus := X; while modulus > 0 loop modulus_copy := modulus; modulus := modulus/2; remainder := modulus_copy rem 2; if modulus >= 1 then if remainder = 1 then remainder_detect := 1; else remainder_detect := remainder_detect; end if; else remainder_detect := remainder_detect; end if; if modulus >= 1 then result := result +1; elsif remainder_detect > 0 then result := result + 1; end if; end loop; return result; end function; end;

Arithmetic conversion functions Need to include std_logic_arith library Need to include std_logic_arith library Conv_integer: converts a std_logic_vector to integer Conv_integer: converts a std_logic_vector to integer –i <= conv_integer(‘0’ & count); Std_logic_vector: converts an integer to std_logic_vector Std_logic_vector: converts an integer to std_logic_vector –count <= std_logic_vector(i, count’length);

ROM entity entity rominfr is port ( clk : in std_logic; en : in std_logic; addr : in std_logic_vector(4 downto 0); data : out std_logic_vector(3 downto 0)); end rominfr;

ROM architecture architecture syn of rominfr is type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0); constant ROM : rom_type := ("0001","0010","0011","0100","0101","0110","0111","1000 ","1001“,"1010","1011","1100","1101","1110","1111","0 001","0010","0011","0100","0101","0110","0111","1000","1001","1010","1011","1100","1101","1110","1111"); begin process (clk) begin if (clk’event and clk = ’1’) then if (en = ’1’) then data <= ROM(conv_integer(addr); end if; end process; end syn;

DUAL –PORT RAM ENTITY entity rams_14 is port ( clk : in std_logic; clk : in std_logic; ena : in std_logic; ena : in std_logic; enb : in std_logic; enb : in std_logic; wea : in std_logic; wea : in std_logic; addra : in std_logic_vector(log(ram_depth)-1 downto 0); addra : in std_logic_vector(log(ram_depth)-1 downto 0); addrb : in std_logic_vector(log(ram_depth)-1 downto 0); addrb : in std_logic_vector(log(ram_depth)-1 downto 0); dia : in std_logic_vector(word_length-1 downto 0); dia : in std_logic_vector(word_length-1 downto 0); doa : out std_logic_vector(word_length-1 downto 0); doa : out std_logic_vector(word_length-1 downto 0); dob : out std_logic_vector(word_length-1 downto 0)); dob : out std_logic_vector(word_length-1 downto 0)); end rams_14;

DUAL –PORT RAM ARCHITECTURE architecture syn of rams_14 is type ram_type is array (ram_depth-1 downto 0) of std_logic_vector(word_length-1 downto 0); type ram_type is array (ram_depth-1 downto 0) of std_logic_vector(word_length-1 downto 0); signal RAM : ram_type; signal RAM : ram_type; signal read_addra : std_logic_vector(log(ram_depth)-1 downto 0); signal read_addra : std_logic_vector(log(ram_depth)-1 downto 0); signal read_addrb : std_logic_vector(log(ram_depth)-1 downto 0); signal read_addrb : std_logic_vector(log(ram_depth)-1 downto 0);begin

DUAL–PORT RAM ARCHITECTURE process (clk) begin begin if (clk'event and clk = '1') then if (clk'event and clk = '1') then if (ena = '1') then if (ena = '1') then if (wea = '1') then if (wea = '1') then RAM (conv_integer(addra)) <= dia; RAM (conv_integer(addra)) <= dia; end if; end if; read_addra <= addra; read_addra <= addra; end if; end if; if (enb = '1') then if (enb = '1') then read_addrb <= addrb; read_addrb <= addrb; end if; end if; end process; end process; doa <= RAM(conv_integer(read_addra)); doa <= RAM(conv_integer(read_addra)); dob <= RAM(conv_integer(read_addrb)); dob <= RAM(conv_integer(read_addrb)); end syn;

Attributes Data attributes(all synthesizable) Data attributes(all synthesizable) –d’LOW --returns lower index –d’HIGH--returns higher index –d’LEFT --returns leftmost index –d’RIGHT--returns rightmost index –d’LENGTH --returns vector size –d’RANGE--returns vector range –d’REVERSE_RANGE --returns reverse vector range Signal attributes(first two synthesizable) Signal attributes(first two synthesizable) –s’EVENT--returns true when event on s –s’STABLE--returns true when no event on s –s’ACTIVE--returns true when s=‘1’ –s’QUIET --returns true when no event on s for specified time –s’LAST_EVENT--returns time since last event on s –s’LAST_ACTIVE--returns time since s = ‘1’ –s’LAST_VALUE--returns value of s before last event

Common VHDL Pitfalls

Name inconsistency Compile: error Compile: error Severity: Trivial Severity: Trivial

Reading an output Compile: Error: cannot read output Compile: Error: cannot read output Solution: Use internal signal Solution: Use internal signal ENTITY counter is PORT(clk, rst_n: in std_logic; PORT(clk, rst_n: in std_logic; count: out std_logic_vector(3 downto 0)); count: out std_logic_vector(3 downto 0)); end counter; Architecture rtl of count is beginPROCESS(clk)begin if clk’event and clk=‘1’ then if clk’event and clk=‘1’ then if rst_n = ‘0’ then –-synchronous reset if rst_n = ‘0’ then –-synchronous reset count ‘0’); count ‘0’); else else if en = ‘1’ then --count enable if en = ‘1’ then --count enable count <= count + ‘1’; --cannot read output error count <= count + ‘1’; --cannot read output error end if; end if; end process;

Multiple unconditional concurrent assignments Simulation: ‘X’ value Simulation: ‘X’ value Synthesis: ERROR: signal is multiply driven Synthesis: ERROR: signal is multiply driven Severity: Serious Severity: Serious Architecture rtl of my_entity is BEGIN output <= a AND b;... output <= b XOR c; Process (b,c) Begin output <= b OR c; End process; End;

Incomplete sensitivity list Simulation: Unexpected behavior Simulation: Unexpected behavior Synthesis: Warning: Incomplete sensitivity list Synthesis: Warning: Incomplete sensitivity list Severity: Serious Severity: Serious Solution: complete sensitivity list Solution: complete sensitivity list PROCESS(a, b) BEGIN d <= (a AND b) OR c; --c is missing from sensitivity list!!! d <= (a AND b) OR c; --c is missing from sensitivity list!!! END PROCESS;

Not assigning all outputs in combinational process Simulation: Simulation: Synthesis: Warning: Signal not always assigned, storage may be needed Synthesis: Warning: Signal not always assigned, storage may be needed Severity: Serious Severity: Serious Solution: assign all signals Solution: assign all signals PROCESS(a, b, c) BEGIN if c = ‘0’ then if c = ‘0’ then d <= (a AND b) OR c; --d assigned only first time, d <= (a AND b) OR c; --d assigned only first time, else else e <= a; --e assigned only second time!!! e <= a; --e assigned only second time!!! END PROCESS;

Unassigned signals Simulation: Undefined value (‘U’) Simulation: Undefined value (‘U’) Synthesis: Warning: Signal is never used/never assigned a value Synthesis: Warning: Signal is never used/never assigned a value Severity: Moderate Severity: Moderate Architecture rtl of my_entity is Signal s: std_logic; Begin Output <= input1 and input2; --s never assigned End;

Output not assigned or not connected Simulation: Undefined Simulation: Undefined Synthesis: Error: All logic removed from the design Synthesis: Error: All logic removed from the design Severity: Serious Severity: Serious ENTITY my_entity IS PORT (input1, input2: in std_logic; output: out std_logic); End my_entity; Architecture rtl of my_entity is Signal s: std_logic; Begin s <= input1 and input2; --output never assigned End;

Using sequential instead of concurrent process Simulation: Unexpectedly delayed signals Simulation: Unexpectedly delayed signals Synthesis: More FFs than expected Synthesis: More FFs than expected