Playstation2 Architecture Architecture Hardware Design

System Overview The listing below is a clean view of the design behind the Playstation2 hardware The listing below is a clean view of the design behind the Playstation2 hardware

CORE CPU General Purpose MIPS variant General Purpose MIPS variant 128bit SIMD integer multimedia extensions 128bit SIMD integer multimedia extensions ICACHE and DCACHE ICACHE and DCACHE Scratch Pad RAM Scratch Pad RAM Dedicated FPU coprocessor Dedicated FPU coprocessor CPU CORE SPR 16 KB I$ 16KB D$ 8KB Emotion Engine FPU

Dedicated FPU FPU – Floating-Point Processing Unit FPU – Floating-Point Processing Unit This unit is used to handle fast floating- point operations This unit is used to handle fast floating- point operations Playstation2 is optimized for 32bit operations. Playstation2 is optimized for 32bit operations. “double” data type or 64bit floating operations are much slower and cause major bottle necks “double” data type or 64bit floating operations are much slower and cause major bottle necks

SIMD SIMD - Single Instruction Multiple Data SIMD - Single Instruction Multiple Data 128bit SIMD allows for a single operation to be applied to four integers / floats 128bit SIMD allows for a single operation to be applied to four integers / floats The operations that can be performed are specific to the CPU The operations that can be performed are specific to the CPU SIMD is especially useful in games for all of it’s complex vector and matrix math SIMD is especially useful in games for all of it’s complex vector and matrix math

How SIMD Works If given two packed data elements the operation is performed to all of the components in each element If given two packed data elements the operation is performed to all of the components in each element

Typical System Layout: Cache Dependency The cache is found on the CPU and has faster access times than system memory The cache is found on the CPU and has faster access times than system memory

CACHE The purpose of cache is to reduce the time it takes to execute redundant operations or access data values The purpose of cache is to reduce the time it takes to execute redundant operations or access data values ICACHE – Instruction Cache ICACHE – Instruction Cache DCACHE – Data Caches DCACHE – Data Caches SPR – Scratch Pad RAM SPR – Scratch Pad RAM

How Cache Works CPU Fetch ICACHE System RAM DCACHE Priority: Cache > System Memory

Hardware Controllers A controller is a device used to interface and communicate with a piece of hardware A controller is a device used to interface and communicate with a piece of hardware Every major component has a controller for their interface Every major component has a controller for their interface The user application will typically use registers or interrupt calls to access the controller devices The user application will typically use registers or interrupt calls to access the controller devices

DMA Controller DMA – Direct Memory Access DMA – Direct Memory Access DMAC is the arbiter for the main bus DMAC is the arbiter for the main bus Used to transfer data between processes Used to transfer data between processes Allows for some parallelism Allows for some parallelism DMA Controller 10 CH CPU CORE I$D$ 128bit

Vector Units Playstation2 has two vector units that are similar but not the same Playstation2 has two vector units that are similar but not the same VU0 is the CPU’s alternate processing unit. VU0 is the CPU’s alternate processing unit. VU1 is the GS’s alternate processing unit VU1 is the GS’s alternate processing unit Each Unit has a direct pipeline to it’s alternate processor Each Unit has a direct pipeline to it’s alternate processor Vector Units are designed for vectors Vector Units are designed for vectors (imagine that)

DMAC and Graphics DMAC feeds VU1 with needed data, and does so with no CPU intervention DMAC feeds VU1 with needed data, and does so with no CPU intervention Data that is transferred to VU1 is resident on system RAM Data that is transferred to VU1 is resident on system RAM CPU is now free to process any instructions that have made hits in the instruction cache CPU is now free to process any instructions that have made hits in the instruction cache CPU can also access any information in the data cache CPU can also access any information in the data cache

VU Architecture VU0/1 each have access to 32 float registers and 16 integer register VU0/1 each have access to 32 float registers and 16 integer register Float registers are not your average PC style registers; they are 128bits in size Float registers are not your average PC style registers; they are 128bits in size 128bits can conveniently fit 4 float values at once (very similar to SIMD architecture) 128bits can conveniently fit 4 float values at once (very similar to SIMD architecture) Integer registers are typically used as loop counters and address calculators Integer registers are typically used as loop counters and address calculators

VU0 VU0 has two bus lines VU0 has two bus lines One bus is dedicated to the CPU One bus is dedicated to the CPU The other bus is used to communicate with all other devices The other bus is used to communicate with all other devices Access to shared bus lines always need to be monitored Access to shared bus lines always need to be monitored VU0 has 4KB of $ VU0 has 4KB of $ VU0 I$ 4KB D$ 4KB CPU CORE SYS RAM shared bus dedicated

Shared Buses and VU0 Why do we need to monitor shared buses? Why do we need to monitor shared buses? –Only one process can access shared devices at a time –Any access operations through a shared bus will cause all other processes to wait Using the VU registers and reducing RAM access will help prevent shared access Using the VU registers and reducing RAM access will help prevent shared access

VU1 VU1 has two bus lines VU1 has two bus lines Main bus is dedicated to the GS Main bus is dedicated to the GS Has almost identical functionality as VU0 Has almost identical functionality as VU0 Main purpose of VU1 is to process the data before the GS Main purpose of VU1 is to process the data before the GS VU1 has 16KB of $ VU1 has 16KB of $ VU1 I$ 16KB D$ 16KB GS CORE SYS RAM shared bus dedicated

Review Playstation2 is like having 4x300 MHz processors Playstation2 is like having 4x300 MHz processors –CPU + VU0 + VU1 + GS Cache utilization is the key to reaching the limits of this system Cache utilization is the key to reaching the limits of this system VU0 is primarily for CPU vector operations VU0 is primarily for CPU vector operations VU1 is dedicated to geometry processing VU1 is dedicated to geometry processing GS manages hardware support of triangle rasterization GS manages hardware support of triangle rasterization