Topics covered: Instruction Set Architecture CSE243: Introduction to Computer Architecture and Hardware/Software Interface

Instruction Set Architecture  Registers and addressing  Addressing modes  Instructions  Assembly language  Branch instructions  Stacks and subroutines  Simple programs in assembly language

2 Registers and addressing  External word length:  Word length used to transfer data between the processor and memory.  16 bits.  Internal word length:  Refers to the size of the processor registers  32 bits.

3 Register structure  8 data registers (D0-D7) and 8 address registers (A0-A7):  Each is 32 bits long.  Instructions use operands of three different lengths:  Long word – 32 bits  Word – 16 bits  Byte – 8 bits  A byte or a word operand stored in a data register is in the low order bit positions of a register:  Most instructions operating on byte or word operands do not affect the higher order bit positions.  Some instructions extend the sign of a shorter operand into the high-order bits.

4 Register structure (contd..)  Address registers hold information used in determining the addresses of memory operands:  Address and data registers can also be used as index registers.  Address register A7 has a special function of serving as the processor stack pointer.  Address registers and calculations involve 32 bits:  Only the least 24 significant bits of an address are used externally to access the memory.  Processor Status Register (SR):  Five condition code bits.  Three interrupt bits (function will be clear when we discuss I/0)  Two mode-select bits.

5 Register structure (contd..) Word Byte Long word registers Data registers Address D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A Supervisor stack pointer User stack pointer SR PC Status register Carry Overflow Zero Negative Trace mode select Supervisor mode select Interrupt mask pointers Stack A7 -T -S -I -Z -N -V -C

6 Addressing Contentsaddresses Word byte 0 byte 2 bytei i+2 byte 1 byte 3 bytei+1 bytei i i+2 Long word 0 Long word i byte byte Byte addressable memory Memory is organized in 16-bit words. Two consecutive 16-bit words constitute one 32-bit long word. Word address must be an even number, that is, words must be aligned on an even boundary. Byte in the high-order position has the same address as the word, the byte in the low-order position has the next higher address. This is the big endian address assignment.

7 Addressing (contd..)  generates 24-bit memory addresses.  Addressable space is 2 24 (16,777,216 or 16M) bytes.  Addressable space may be thought of as consisting of:  512 (2 9 ) pages of 32K (2 15 ) bytes each.  Page 0 is hexadecimal addresses 0 to 7FFF.  Page 1 is hexadecimal addresses 8000 to FFFF.  Last page is hexadecimal addresses FF8000 to FFFFF.

8 Addressing modes  Instruction size:  Many instructions are one word (16-bit long), some require additional 16-bit words for extra addressing information.  First word of an instruction is the OP-code word.  Subsequent words (if any) are called extension words.  Note that the does not place a one word limit on the instruction size, it is a CISC architecture.  Immediate mode  Operand is included in the instruction.  Byte, word, long-word operands are specified in the extension word.  Some very small operands are included in the OP-code word.

9 Addressing modes (contd..)  Absolute mode:  Absolute address of an operand is given in the extension word.  Long mode: 24-bit address is specified.  Short mode: 16-bit value is specified, which serves as the low- order 16 bits of an address. Sign bit of the 16-bit value is extended to provide the high- order 8 bits. Sign-bit is 0 or 1, so two pages can be addressed: 0, and FF8.  Register mode:  Operand is in a processor register specified in the instruction.  Register indirect mode:  Effective address (EA) of an operand is in a processor register which is specified in an instruction.

10 Addressing modes (contd..)  Autoincrement mode:  EA is in one of the address registers which is specified in the instruction.  After the operand is addressed, the contents of the address register are incremented by 1 (byte), 2 (word), 4 (long-word).  Autodecrement mode:  Same as above, except the contents are decremented before the operand is accessed.  Basic index mode:  16-bit signed offset and an address register are specified.  Full index mode:  8-bit signed offset, an address register and an index register (either a data or address register) are specified.  Basic relative and Full relative modes:  Same as Basic index and Full index modes respectively, except PC is used instead of address register.

11 Addressing modes (contd..) Array 6 = index 100 = offset A Extension word OP-code word Operand Consider the instruction: ADD 100(PC,A1), D0 Full relative mode for the source operand. Register mode for the destination operand. Compute the EA of the source operand: - Suppose A1 holds the value 6. - Suppose the OP-code word is at After the OP-code word is fetched, PC points to the extension word, i.e EA = [PC] + [A1] Thus, EA is This could be used to address the data in an array form. In relative modes, PC need not be specified explicitly in the instruction.

12 Instructions  Extensive set of instructions.  Both two-operand and one-operand instructions.  Two-operand instructions:  Format: OP src, dst.  Assembly language notation, the actual encoding may not be in the same order.  OP specifies the operation performed.  Result is placed in the destination location.  For most two operand instructions, either src, or dst operand must be in a data register. Other operand may be specified using any one of the addressing modes.  The only two operand instruction where any addressing mode may be used to specify both the operands is the MOVE instruction.

13 Instructions (contd..) Consider the instruction: ADD #9, D3 Add 9 to contents of D3 and store result in D3. src1011dst0 operation size Bits and 8 specify the operation. Bits 9-11 specify the destination register D3. Bits 7-5 specify the size of the operands, default is word, with a bit pattern 01. Bits 5-0 identifies that the source operand is immediate with the pattern The actual value of the source operand is in the extension word. CD76Hex Binary Binary and hex encoding of the OP-code word are shown.

14 Instructions (contd..) Consider the instruction: ADD #9, D3 Add 9 to contents of D3 and store result in D3. D3 PC 9 D67C i + 4 i + 2 i Before instruction fetch After instruction execution 2534 PCii + 4 Immediate operand OP-code word D3 OP-code word is at location i. Operand 9 is in the extension word at location i+2. After the OP-code word is fetched PC points to i+2. After the extension word is fetched, PC points to i+4. Contents of D3 before execution are 25, and after execution are 34.

15 Assembly language  Instructions can operate on operands of three sizes, size of the operands must be indicated:  Size of the operand is indicated in the operation mnemonic, using L for long-word, W for word, and B for byte.  ADD.L indicates ADD operation with operand size long-word.  Representation of numbers:  Default representation is in the decimal form.  Prefix $ is used for hexadecimal, and % for binary.  Representation of Alphanumeric characters:  Placed within quotes, replaced by the assembler with their ASCII codes.  Several characters may be placed in a string between quotes.

16 Assembler directives  ORG: Starting address of an instruction or data block.  EQU: Equating names with numerical values  DC (Define Constant): Data constants.  Size indicator may be appended to specify the size of the data constants. DC.B, DC.W, DC.L.  DS (Define Storage): Reserve a block of memory.  Names can be associated with memory locations using labels as described earlier.

17 Condition code flags  Five condition code flags, stored in the status register.  N  Z  V  C  X – Extend flag, set the same way as C flag, but not affected by many instructions. Useful for precision arithmetic.  Since operands can be of three sizes (byte, word and long- word):  C and X flags depend on the carry-out from bit positions 7, 15 and 31.

18 Branch instructions  Recall that a conditional branch instruction causes program execution to continue with the instruction at the branch target address if the condition is met, else the instruction immediately following the branch is executed.  Branch target address is computed by adding an offset to the PC.  Branch instructions with two types of offset, 8 and 16 bit.  Branch instructions with 8-bit offset:  Offset is included in the OP-code word.  Branch target address is within –127 to 128 of the value in PC.  PC contents are incremented at each fetch, offset defines the distance from the word that follows the branch instruction OP- code word.

19 Branch instructions (contd..)  Branch instructions with a 16-bit offset:  Offset is specified in an extension word following the OP-code word.  Branch target address can be in the range of +32K to –32K from the value in PC.  Offset is the distance from the extension word to the branch target.  16 conditional branch instructions, each with two offsets.  1 unconditional branch instruction.

20 Stacks and subroutines  Stack can be implemented using any of the address registers, with the help of autoincrement and autodecrement addressing modes.  Register A7 is designated as the processor stack pointer, and it points to the processor stack.  Stack used by the processor for all operations that it performs automatically, such as subroutine linkage.  Two different stack pointer registers, for two modes of operation:  Supervisor mode: All machine instructions can be executed.  User mode: Certain privileged instructions cannot be executed.  Application programs: user mode.  System software: supervisor mode.

21 Stacks and subroutines (contd..)  Stack may be used for:  Subroutine linkage mechanism.  Passing parameters to a subroutine and returning result from the subroutine.  Branch-to-Subroutine (BSR) is used to call a subroutine:  Causes the contents of the PC to be pushed onto the stack.  Return from Subroutine (RTS) is used to return from a subroutine:  Causes the return address at the top of the stack to be popped into the PC.

22 Simple programs in assembly language. Add the contents of memory locations A and B, and place the result in C. Size of operands A and B is word. Recall that: - For a two-operand instruction, one of the operands has to be placed in a data register D0 through D7. MOVE A, D0 Move A to register D0. ADD B, D0 Add the contents of location B to D0 and store the result in D0. MOVE D0, C Transfer the result in register D to location C.

23 Simple programs in assembly language C = B = A = E 20120C 20120A OP-code word OP-code word OP-code word 20 MOVE A,D0 ADD B,D0 MOVE D0,C After execution, [202200] = 424 Add the contents of A and B, and place the result in location C. Size of the operands at locations A and B is 16 bits. A, B, and C and the program to add is stored in the memory

24 Simple programs in assembly language MemoryAddressing addressordata labelOperationinformation AssemblerdirectivesCEQU$ ORG$ ADC.W639 BDC.W215 ORG$ StatementsthatMOVEA,D0 generatemachineADDB,D0 instructionsMOVED0,C AssemblerdirectiveEND – Program to add A and B, and store the result in C with assembler directives.

25 Simple programs in assembly language. Add N numbers: - The first number is stored at the starting address NUM1. - The count of entries to be added is stored at address N. - Store the result at location SUM. - Size of each number to be added is Word. MOVE.LN,D1Ncontainsn,thenumberofentries tobeadded,andD1isusedas acounterthatdetermineshow manytimestoexecutetheloop. MOVEA.L#NUM1,A2A2isusedasapointertothelistentries. ItisinitializedtoNUM1,theaddress ofthefirstentry. CLR.LD0 isusedtoaccumulatethesum. LOOPADD.W(A2)+,D0SuccessivenumbersareaddedinD0. SUBQ.L#1,D1Decrementthecounter. BGTLOOPIf[D1]>0,executetheloopagain. MOVE.LD0,SUMStorethesuminSUM.