Presentation is loading. Please wait.

Presentation is loading. Please wait.

EET 2261 Unit 2 HCS12 Architecture

Similar presentations


Presentation on theme: "EET 2261 Unit 2 HCS12 Architecture"— Presentation transcript:

1 EET 2261 Unit 2 HCS12 Architecture
Read Almy, Chapters 3, 4, and 5. Homework #2 and Lab #2 due next week. Quiz next week. Handouts: Quiz 1, Instruction Summary practice sheet, Addressing Modes practice sheet, Condition Code practice sheet.

2 Condition Code Register
CPU Programming Model Inside any processor’s CPU are certain registers that the programmer has access to. The list of these registers is often called the CPU programming model. For the HCS12: Register Number of bits Accumulator A 8 Accumulator B Accumulator D 16 Index Register X Index Register Y Stack Pointer Program Counter Condition Code Register

3 HCS12 CPU Programming Model
See page 30 of textbook or page 375 of CPU Reference Manual.

4 Purposes of the Registers
Accumulators A, B, and D are general-purpose registers that the programmer can use however she wants. PC and CCR are special-purpose registers that always perform specific functions: PC always holds the address of the next instruction to be executed. CCR always holds three mask bits and five status flags. The other registers (X, Y, and SP) sometimes serve as general-purpose registers and sometimes perform specific functions.

5 Accumulators A, B, and D The HCS12 has two 8-bit accumulators, named A and B. These two can also be regarded as forming a single 16-bit accumulator named D. Some instructions operate on Accumulator A or Accumulator B. Other instructions operate on Accumulator D. Examples: LDAA loads an 8-bit number into A. LDAB loads an 8-bit number into B. LDD loads a 16-bit number into D.

6 HCS12 Instruction Set A processor’s instruction set is the list of instructions (or commands) that the CPU recognizes. Most of these instructions manipulate the CPU’s registers or locations in memory (or both).

7 Instruction Set Summary
For a summary of the HCS12’s instruction set, see the table on pages of the CPU Reference Manual.

8 Example: ABA This table uses many abbreviations and special symbols. They’re all explained in the pages before the table (pages of the CPU Reference Manual.) Let’s look at one instruction, ABA, which adds Accumulator B to Accumulator A and puts the results in Accumulator A.

9 First Column: Source Form
This column shows how you’ll type the instruction when you start writing assembly language programs next week. ABA is very simple. Other instructions are more complicated and have additional things you need to type, explained here:

10 Second Column: Operation
This column explains the operation that the instruction performs. Some symbols used in this column:

11 Third Column: Addressing Mode
This column shows the addressing mode(s) used by the instruction. As we’ll see below, there are six different addressing modes. Some abbreviations used in this column:

12 Fourth Column: Machine Coding
Computers use numbers to represent all kinds of information, including the instructions in a program. This column shows the numbers (in hex) that represent each instruction. Some abbreviations used in this column:

13 Fifth Column: Access Detail
This column shows how many cycles each instruction takes to execute, and what happens during each of those cycles. Some abbreviations used in this column: The only thing we’ll care about is the number of cycles required for a particular instruction to execute.

14 Last Two Columns: Condition Codes
These columns show how each instruction affects the bits in the Condition Code Register. Symbols used in these columns: Start a new project in CodeWarrior, go into the debugger, place an ABA instruction at $2000, set the PC to $2000, set values in A and B, and single-step.

15 Summary This table summarizes a lot of useful information for every one of the 207 instructions that you can use when writing programs for the HCS12. You’ll refer to this table often. Do practice sheet on instructionSummary.

16 Instruction Set Details
For details on all 207 of the HCS12’s instructions, see pages of the CPU Reference Manual.

17 RISC Architecture versus CISC Architecture
Some commercially available microprocessors use a RISC (Reduced Instruction Set Computer) architecture. Small instruction set (maybe 25 or 30 instructions). Each instruction performs a simple operation and executes quickly. The HCS12 is an example of a CISC (Complex Instruction Set Computer) processor. Large instruction set (207 in the HCS12’s case). Some instructions perform complex operations that might require a dozen or more instructions in a RISC processor. There’s a lot of debate over which architecture is better.

18 Categories of Instructions
The Instruction Set Summary table lists instructions alphabetically. Sometimes it’s more useful to have instructions grouped into categories of similar instructions. Examples of categories: Load and Store Instructions Addition and Subtraction Instructions Boolean Logic Instructions See Section 5 (starting on p. 55) of the CPU Reference Manual. The manual’s categories are very similar to, but not exactly the same as, the textbook’s categories on pages and in Chapters 6 – 11.

19 Mnemonics In this course we’ll write programs in a language called assembly language. Assembly language contains many mnemonics, which are abbreviations for actions that we want to perform. (Mnemonics appear in the Source Form column of the Instruction Set Summary.) Some examples: Mnemonic Action ABA Add Accumulator B to Accumulator A LDAA Load Accumulator A with a number STAA Store Accumulator A into memory

20 Operands Some HCS12 instructions require the programmer to specify one or two operands, in addition to the mnemonic. These operands are the data (usually numbers) to be operated on. Example: The LDAA instruction loads some number into accumulator A. The number that’s to be loaded is the operand. In the instruction LDAA #5, the operand is 5. But there are other ways to specify the operand. For example, instead of specifying the number to be loaded right in the instruction itself, maybe we want to load the number from a particular memory location into ACCA.

21 Opcodes When an instruction is translated into machine code, the mnemonic is replaced by an opcode. Example: The assembly-language instruction LDAA #5 becomes $ in machine code, because $86 is the opcode for LDAA. Mnemonic Operand Opcode

22 Review: Memory Addresses
Every computer system has memory, where programs and data are stored. Each location within this memory has an address by which we identify it. And each location holds some contents, which is one byte. The HCS12 uses a 16-bit address bus. So the addresses of its memory locations range from $0000 to $FFFF. (In decimal, that’s 0 to 65,535.) So we have 65,536 memory locations, each of which holds one byte.

23 Review: Memory Map Programmers must pay attention to where in memory their programs and data are stored. Some of a system’s memory is reserved for special purposes. Therefore, within the range of possible addresses, only some can be used by your programs. A memory map shows which memory addresses are reserved, and which are available for your use. Next slide shows memory map for our HCS12 chip.

24 HCS12 Memory Map See page 26 of Device User Guide. Reserved addresses:
$0000 to $03FF are reserved for special-function registers. $FF00 to $FFFF are reserved for interrupt vectors.

25 Addressing Modes Every instance of an instruction uses an addressing mode. The HCS12’s six addressing modes are: Inherent Immediate Direct Extended Indexed (which has several variations) Relative

26 Which Addressing Mode(s) Does an Instruction Use?
Some instructions come in only one “flavor”: they can only use one addressing mode. Example: The ABA instruction always uses the inherent addressing mode. Other instructions come in two or more “flavors.” Example: The LDAA instruction can use immediate, direct, extended, or indexed addressing. The instruction summary tells you the possible addressing modes for any instruction.

27 Inherent Addressing Mode
In inherent addressing mode, the programmer doesn’t specify any operands, because the mnemonic itself contains all of the information needed. Example: The ABA instruction adds the numbers in Accumulators A and B. So we already know where the two operands are located, and we don’t need to say any more. We just write ABA, instead of writing something like ABA #5.

28 Immediate Addressing Mode
In immediate addressing mode, the programmer gives the operand(s) as part of the instruction. The pound sign (#) indicates immediate addressing. Example: LDAA #15 causes the number 15 to be loaded into Accumulator A. The following are all equivalent: LDAA #15 LDAA #$F LDAA #%1111 In CodeWarrior, hand-code and run an LDAA #15.

29 Direct Addressing Mode
In direct addressing mode, the programmer gives the operand’s address as part of the instruction. Example: LDAA 51 causes the number located at memory address 51 to be loaded into Accumulator A. The following are all equivalent: LDAA 51 LDAA $33 LDAA % In CodeWarrior, hand-code and run an LDAA 51.

30 Limitation of Direct Addressing Mode
In direct addressing mode, the operand’s address can only be one byte long. So the highest address we can use with direct addressing is $FF, or 255. Since there are 65,536 locations in memory, this means that 65,281 of those locations can’t be reached by direct addressing! Solution: use extended addressing mode instead of direct addressing mode. (See next slide.)

31 Extended Addressing Mode
In extended addressing, the programmer gives the operand’s address as part of the instruction (just as in direct addressing). But this address is two bytes long, so we can reach any memory location. Example: LDAA $701F causes the number located at memory address $701F to be loaded into Accumulator A. The following are all equivalent: LDAA 28703 LDAA $701F LDAA %

32 Summary: Addressing Modes
We’ve discussed the first four of the HCS12’s six addressing modes: Inherent Immediate Direct Extended Indexed (which has several variations) Relative We’ll discuss the other two modes in the weeks ahead. Do addressingModes practice sheet.

33 Condition Code Register
The Condition Code Register (CCR) is an 8- bit register that contains: 5 flag bits (H, N, Z, V, C) 2 interrupt mask bits (X and I) STOP instruction control bit (S)

34 Meanings of the H, Z, and C Flag Bits
The flag bits are set or reset based on the results of previously executed instructions. H=1 if a half-carry (carry from bit 3 to bit 4) occurred. Z=1 if the result was zero. C=1 if a carry out of the leftmost bit occurred (or, in the case of subtract instructions, if a borrow into the leftmost bit occurred). But only some instructions affect these flag bits: check the instruction summary table. Do conditionCode practice sheet for H, Z, C bits.

35 Review: Two’s-Complement Notation
Recall that two’s-complement notation is the standard way of representing signed numbers in binary. In this notation, the leftmost bit is the sign bit. Sign bit = 0 for positive numbers or 0. Sign bit = 1 for negative numbers. Examples, using 8 bits: % = 3 % = 125

36 Meanings of the N and V Flag Bits
N=1 if the result’s leftmost bit (MSB) was 1. If you’re using signed numbers, this means that the result was negative. V=1 if a two’s-complement overflow occurred. This happens when either: We added two positive numbers (MSB=0) and got a negative result (MSB=1). Or we added two negative numbers (MSB=1) and got a positive result (MSB=0). Again, only some instructions affect these flag bits: check the instruction summary table. Do conditionCode practice sheet for N, V bits.


Download ppt "EET 2261 Unit 2 HCS12 Architecture"

Similar presentations


Ads by Google