1. Computer Organization and Assembly Language (COAL)
Lecture # 7,8,9
25th- - 29th Shawwal 1434 / 2nd – 6th September 2013

2. This Week’s Objectives
Read Text Book Ch # 2 (2.1, 2.2, – 2.3.3)
Machine instructions and program execution
Addressing methods for accessing register and memory operands
Assembly language for representing machine instructions, data, and programs

3. Memory Locations and Addresses
Memory consists of many millions of storage cells, each of which can store a bit of information having the value 0 or 1.
Because a single bit represents a very small amount of information, bits are seldom handled individually.
The usual approach is to deal with them in groups of fixed size.
For this purpose, the memory is organized so that a group of n bits can be stored or retrieved in a single, basic operation.
Each group of n bits is referred to as a word of information, and n is called the word length.
The memory of a computer can be schematically represented as a collection of words.

4. If the word length of a computer is 32 bits, a single word can store a 32-bit signed number or four ASCII-encoded characters, each occupying 8 bits.
Machine instructions may require one or more words for their representation.
Accessing the memory to store or retrieve a single item of information, either a word or a byte, requires distinct names or addresses for each location.
It is customary to use numbers from 0 to 2k − 1, for some suitable value of k, as the addresses of successive locations in the memory.
The memory can have up to 2k addressable locations that constitute the address space of the computer.

5. Word Length Addresses Address Space
A 24-bit address generates an address space of M (16,777,216) locations. 1M = 220 (1,048,576).
A 32-bit address creates an address space of 232 or 4G (4 giga) locations, where 1G is 230.

7. Byte Addressability
Successive addresses refer to successive byte locations in the memory. The term byte-addressable memory is used for this assignment. Byte locations have addresses 0, 1, 2,
Therefore, for word length of 32 bits, successive words are located at addresses 0, 4, 8, , with each word consisting of four bytes.

8. Word Alignment
In the case of a 32-bit word length, natural word boundaries occur at addresses 0, 4, 8, ,.
We say that the word locations have aligned addresses if they begin at a byte address that is a multiple of the number of bytes in a word.
The number of bytes in a word is a power of 2.
16 bits aligned words begin at byte addresses 0, 2, 4, , and 64 bits aligned words begin at byte addresses 0, 8, 16, , and so on.
Using aligned addresses makes accessing of memory operands more efficient.

9. Big-Endian and Little-Endian Assignments
There are two ways that byte addresses can be assigned across words.
The name big-endian is used when lower byte addresses are used for the more significant bytes (the leftmost bytes) of the word.
The name little-endian is used for the opposite ordering, where the lower byte addresses are used for the less significant bytes (the rightmost bytes) of the word.
The words “more significant” and “less significant” are used in relation to the weights (powers of 2) assigned to bits when the word represents a number.
Both little-endian and big-endian assignments are used in commercial machines.
In both cases, byte addresses 0, 4, 8, , are taken as the addresses of successive words in the memory

10. Big-Endian and Little-Endian
Given the hex number

12. Memory Operations
Already discussed in the previous week. Figure 1.2 page 8 Chapter # 1 of the text book.
Topics covered were:
Busses (Address bus, Data bus, Control Bus)
Read and Write control signals
Memory read operations while executing MOV AX, [23FEh]
Memory write operation while executing MOV [87FFh], BX

13. Type of Instruction in a Processor
A computer must have instructions capable of performing four types of operations:
Data transfers between the memory and the processor registers
Arithmetic and logic operations on data
Program sequencing and control
I/O transfers

14. Register Transfer Notation (1)
In order to describe the transfer of information from one location in a computer to another, we identify such locations symbolically with convenient names.
For example, names that represent the addresses of memory locations may be LOC, PLACE, A, or VAR2. Predefined names for the processor registers may be R0 or R5. Registers in the I/O subsystem may be identified by names such as DATAIN or OUTSTATUS.

15. Register Transfer Notation (2)
To describe the transfer of information, contents of any location are denoted by placing square brackets around its name. Thus, the expression R2 ← [LOC] means that the contents of memory location LOC are transferred into processor register R2.
Similarly, the operation to adds the contents of registers R2 and R3, and places their sum into register R4 is indicated as R4 ← [R2] + [R3].
This type of notation is known as Register Transfer Notation (RTN).

16. Assembly Language Notation
Another type of notation to represent machine instructions and programs is called assembly language.
Assembly Language instructions of processors are defined by using mnemonics, which are typically abbreviations of the words describing the operations.
Assembly languages for different processors have different mnemonics for a given operation.
We will cover Intel’s IA-32/64. E.g. MOV AX, BX, ADD AX, 23Fh, SUB AX, [23h]

20. 8088/8086 Data Addressing Modes

21. Direct Addressing

22. Direct Addressing

23. Register Indirect Addressing

24. Register Indirect Addressing

25. Register Indirect Addressing
MOV AL,[DI]
MOV [DI],10H (?????)
MOV BYTE PTR [DI], 10H
MOV WORD PTR [DI], FC10H
MOV DWORD PTR [DI], AEFC0001H

26. Register Indirect Addressing

27. Register Indirect Addressing

28. Register Indirect Addressing

29. Information (operand) involved in any operation performed by the CPU needs to be addressed.
Instruction issued by the processor must carry at least two types of information.
These are the operation to be performed, encoded in what is called the op-code field.
The address information of the operand on which the operation is to be performed, encoded in what is called the address field.

30. Instructions can be classified based on the number of operands as: three-address, two-address, one-and-half-address, one-address, and zero-address.
Operation represents the operation to be performed, for example, add, subtract, write, or read.
The source field represents the source operand(s).
The source operand can be a constant, a value stored in a register, or a value stored in the memory.
The destination field represents the place where the result of the operation is to be stored, for example, a register or a memory location.

31. A three-address instruction takes the form operation add-1, add-2, add-3
In this form, each of add-1, add-2, and add-3 refers to a register or to a memory location.
For example, the instruction ADD R1, R2, R3.
A three-address instruction that refers to memory locations may take the form ADD A,B,C.
The instruction adds the contents of memory location A to the contents of memory location B and stores the result in memory location C.

32. A two-address instruction takes the form operation add-1, add-2.
In this form, each of add-1 and add-2 refers to a register or to a memory location.
For example, ADD R1, R2
ADD A , B

33. one-address instruction

34. ADD B, R1. In this case, the instruction adds the contents of register R1 to the contents of memory location B and stores the result in register R1. The instruction uses two types of addressing, that is, a register and a memory location, it is called a one-and-half-address instruction. This is because register addressing needs a smaller number of bits than those needed by memory addressing.

35. zero-address instructions
These are the instructions that use stack operation.
A stack is a data organization mechanism in which the last data item stored is the first data item retrieved.
Two specific operations can be performed on a stack.
These are the push and the pop operations.

36. A specific register, called the stack pointer (SP), is used to indicate the stack location that can be addressed.
In the stack push operation, the SP value is used to indicate the location (called the top of the stack) in which the value (5A) is to be stored (in this case it is location 1023). After storing (pushing) this value the SP is incremented to indicate to location 1024.
In the stack pop operation, the SP is first decremented to become 1021.
The value stored at this location (DD in this case) is retrieved (popped out) and stored in the shown register.

38. Different operations can be performed using the stack structure.
Consider, for example, an instruction such as ADD (SP)+, (SP).
The instruction adds the contents of the stack location pointed to by the SP to those pointed to by the SP + 1 and stores the result on the stack in the location pointed to by the current value of the SP.

40. Addressing modes
The different ways in which operands can be addressed are called the addressing modes.
Addressing modes differ in the way the address information of operands is specified.
The simplest addressing mode is to include the operand itself in the instruction, that is, no address information is needed.
This is called immediate addressing.

41. According to this addressing mode, the value of the operand is (immediately) available in the instruction itself.
Consider, for example, the case of loading the decimal value 1000 into a register Ri.
This operation can be performed using an instruction such as the following:
LOAD #1000, Ri.
In this instruction, the operation to be performed is to load a value into a register.
The source operand is (immediately) given as 1000, and the destination is the register Ri.

42. Direct (Absolute) Mode
According to this addressing mode, the address of the memory location that holds the operand is included in the instruction.
Consider, for example, the case of loading the value of the operand stored in memory location 1000 into register Ri.
This operation can be performed using an instruction such as LOAD 1000, Ri.
In this instruction, the source operand is the value stored in the memory location whose address is 1000, and the destination is the register Ri.

44. If the content of the memory location whose address is 1000 was (2345) at the time when the instruction LOAD 1000, Ri is executed, then the result of executing such instruction is to load the value (2345) into register Ri.

45. Indirect Mode
In the indirect mode, what is included in the instruction is not the address of the operand, but rather a name of a register or a memory location that holds the (effective) address of the operand.
In order to indicate the use of indirection in the instruction, it is customary to include the name of the register or the memory location in parentheses.
Consider, for example, the instruction LOAD (1000), Ri.
This instruction has the memory location 1000 enclosed in parentheses, thus indicating indirection.

46. The meaning of this instruction is to load register Ri with the contents of the memory location whose address is stored at memory address 1000.
Because indirection can be made through either a register or a memory location, therefore, we can identify two types of indirect addressing.
These are register indirect addressing, if a register is used to hold the address of the operand, and memory indirect addressing, if a memory location is used to hold the address of the operand.

48. Indexed Mode
In this addressing mode, the address of the operand is obtained by adding a constant to the content of a register, called the index register.
Consider, for example, the instruction LOAD X(Rind), Ri.
This instruction loads register Ri with the contents of the memory location whose address is the sum of the contents of register Rind and the value X.
Index addressing is indicated in the instruction by including the name of the index register in parentheses and using the symbol X to indicate the constant to be added.

50. Relative addressing is the same as indexed addressing except that the program counter (PC) replaces the index register.
For example, the instruction LOAD X(PC), Ri loads register Ri with the contents of the memory location whose address is the sum of the contents of the program counter (PC) and the value X.
Figure 2.9 illustrates the relative addressing mode.

53. Thank You