Timothy O. Dickson and Sorin P. Voinigescu Edward S. Rogers, Sr. Dept of Electrical and Computer Engineering University of Toronto CSICS November 15, 2006 Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

Dickson & Voinigescu 2006 CSICS November 15, 2006 Outline Motivation High-speed, low-power design techniques 2.5-V, 80-Gb/s BiCMOS Transmitter Measurement results Conclusions

Dickson & Voinigescu 2006 CSICS November 15, 2006 Next Generation High-Speed Wireline: 100-Gb/s Ethernet New design challenges as fundamental frequencies enter mm-wave regime 1 x 100-Gb/s

Dickson & Voinigescu 2006 CSICS November 15, 2006 Power Consumption State-of-the-art High-Speed Transceivers Technology130-nm CMOSSiGe (120-GHz f T ) Data Rate3.125-to-10.7-Gb/s2.7-to-43-Gb/s IntegrationSingle-chipChip set Power consumption800 mW12 W ReferenceAeluros, ISSCC 2004Big Bear, ISSCC 2003 should consume less power than 100 Gb/s 10 x 10 Gb/s

Dickson & Voinigescu 2006 CSICS November 15, 2006 Power Consumption 100-Gb/s 4:1 MUX? TechnologySiGe (210-GHz f T ) Data Rate132-Gb/s Supply Voltage-3.3V Power consumption1.45 W ReferenceIBM, ISSCC 2004 should consume less power than

Dickson & Voinigescu 2006 CSICS November 15, 2006 MOSFETs vs HBTs peak-f T V BE = 900mV… and does not scale! 130-nm peak-f T V GS = 750mV… and decreasing!

Dickson & Voinigescu 2006 CSICS November 15, 2006 Power reduction techniques 43-GHz latch consumes only 20mW BiCMOS logic family reduces supply voltage Reduce tail current with inductive peaking L P = CLV2CLV2 3.1 I T 2 Stacked inductors 10  m

Dickson & Voinigescu 2006 CSICS November 15, 2006 Transmitter Block Diagram 8:1 MUX Output Driver On-chip PRBS for BIST 40-GHz PLL

Dickson & Voinigescu 2006 CSICS November 15, V, 87-Gb/s BiCMOS Selector EF for higher bandwidth SF for voltage headroom 86-Gb/s selector consumes 60mW

Dickson & Voinigescu 2006 CSICS November 15, V, 80-Gb/s BiCMOS Pre-Emphasis Driver MOS gm and input capacitance relatively constant as bias current changes. Excellent for output stages with adjustable amplitude control.

Dickson & Voinigescu 2006 CSICS November 15, V, 80-Gb/s BiCMOS Pre-Emphasis Driver 130-nm MOSFETs switching at 80-Gb/s!

Dickson & Voinigescu 2006 CSICS November 15, V, 80-Gb/s BiCMOS Pre-Emphasis Driver Adjustable pre-emphasis for operation up to 80-Gb/s Boosts high-frequency content to compensate for line losses. Output match S22 < -10dB up to 94 GHz.

Dickson & Voinigescu 2006 CSICS November 15, GHz Colpitts VCO SiGe HBTs used as negative resistance generators. Differential tuning to reject common-mode noise. Maximize tank swing, bias HBTs at NF MIN for low phase noise MHz offset

Dickson & Voinigescu 2006 CSICS November 15, 2006 Die Photograph 1.5 mm 1.8 mm PRBS + 8:4 MUX 4:1 MUX + Output Driver PLL

Dickson & Voinigescu 2006 CSICS November 15, 2006 Measured Results: 80-Gb/s Running for more than 1 hour continuously in the lab. Jitter: 560 fs (rms), Rise/fall time: 4-5 ps, Amplitude: 300 mV

Dickson & Voinigescu 2006 CSICS November 15, 2006 Verification of Correct Multiplexing Using pattern capture capabilities of the Agilent 86100C DCA

Dickson & Voinigescu 2006 CSICS November 15, 2006 Verification of Correct Multiplexing Examine the tone spacing using Agilent E4448A PSA

Dickson & Voinigescu 2006 CSICS November 15, Gb/s: Amplitude Control Little degradation in eye quality as amplitude varies from 100mV to 300 mV per side

Dickson & Voinigescu 2006 CSICS November 15, 2006 Maximum Data Rate: 87-Gb/s 87 GHz 127 = 685 MHz 685 MHz

Dickson & Voinigescu 2006 CSICS November 15, 2006 Maximum Data Rate vs. Temp. 0 o C 100 o C

Dickson & Voinigescu 2006 CSICS November 15, 2006 Comparison Technologyf T /f MAX Data Rate Supply Voltage Power 130-nm CMOS85/90 GHz40-Gb/s (half-rate)1.5 V2.7 W InP HBT150/150 GHz43-Gb/s (full-rate)-3.6/ -5.2 V3.6 W 180-nm SiGe BiCMOS HBT: 120/100 GHz43-Gb/s (half-rate)-3.6 V1.6 W 180-nm SiGe BiCMOS HBT: 120/100 GHz43-Gb/s (full-rate)-3.6 V2.3 W 130-nm SiGe BiCMOS MOS: 85/90 GHz HBT: 150/150 GHz 87-Gb/s (half-rate)2.5 V1.36 W

Dickson & Voinigescu 2006 CSICS November 15, 2006 Conclusions Described methods for power reduction in high-speed building blocks. Use BiCMOS topology to lower supply voltage. Trade off bias current for inductive peaking. Applied these principles to the design of the first 87-Gb/s serial transmitter, which consumes less power than any 40-Gb/s TX reported to date. As compared with state-of-the-art CMOS, this work shows that you can achieve double the data rate with half the power dissipation simply by adding the SiGe HBT option.

Dickson & Voinigescu 2006 CSICS November 15, 2006 Acknowledgements STMicroelectronics Crolles for chip fabrication STMicroelectronics, Gennum, CITO, and NSERC for financial support CMC for CAD tools CFI and OIT for equipment and test support

Dickson & Voinigescu 2006 CSICS November 15, 2006 Questions?

Backups

DC Considerations V GS V BE V DS = 0V! Need CM resistor in 43-GHz clock buffer

Dickson & Voinigescu 2006 CSICS November 15, 2006 Future Directions: Futher Power Savings Reduce supply voltage to 1.8V by removing current sources. 38% power savings would result in 86-Gb/s TX that consumes 825 mW.

Dickson & Voinigescu 2006 CSICS November 15, 2006 SiGe Building Block Supply Voltage DC drops dictate at least 3.3-V supply voltage 150 mV IR 900 mV V BE 750 mV V CE 600 mV V CE + IR Unlike CMOS, supply voltage does not scale!!

Dickson & Voinigescu 2006 CSICS November 15, 2006 CMOS vs. SiGe BiCMOS SiGe HBT has 2-generation speed advantage