1. October 31st, 2005CSICS Presentation1 A 1-Tap 40-Gbps Decision Feedback Equalizer in a 0.18-  m SiGe BiCMOS Technology Adesh Garg, Anthony Chan Carusone and Sorin P. Voinigescu University of Toronto

2. October 31st, 2005CSICS Presentation2 Motivation ■ Electrical equalization has been found to be an effective way to mitigate PMD limited fibre optical channels ■ Linear equalizer can be paired with a decision feedback equalizer (DFE) to further extend the transmission range and/or increase the data rates ■ State of the art ► FFE demonstrated at speeds over 40-Gbps in silicon ► DFE demonstrated only recently at speeds up to 10-Gbps in 0.13  m CMOS as well as a 0.18  m SiGe BiCMOS Goal: To design a 1-Tap DFE at 40-Gbps

3. October 31st, 2005CSICS Presentation3 Architecture ■ Direct Feedback – filter processing in feedback path ► Disadvantages: ● Multiple processing stages in feedback path ● Additional loading at summing node ■ Look-ahead – parallel computation of filter ► Advantages: ● Parallelism employed to remove processing in feedback path ● Limits loading on summing node

4. October 31st, 2005CSICS Presentation4 Architecture ■ Implementation of the architecture requires considerable overhead within the clock distribution ■ Clock path requires the highest bandwidth ► Difficult design ► Power intensive ■ The retimers are replaced with slicers at the inputs of the selector to ease requirements on the clock distribution

5. October 31st, 2005CSICS Presentation5 Circuit Description

6. October 31st, 2005CSICS Presentation6 Circuit Description: Broadband Front End ■ Shunt-Series Input Buffer (TIA) ► Shunt feedback allows for broadband frequency response while matching to 50  ► Resistive degeneration (Series feedback) employed to further improve input linearity ► Allows low noise bias without significantly limiting bandwidth

7. October 31st, 2005CSICS Presentation7 Circuit Description: Broadband Front End ■ Threshold adjustment functionality ► Transition is “strengthened” with variable threshold ► Allows detection of missed bits Input Output

8. October 31st, 2005CSICS Presentation8 Circuit Description: Broadband Front End ■ Threshold Adjustment Buffer ► High Speed Buffer ● linearity ► DC offset ● linear tuning with control voltage ► Adjust threshold up to 225mV

9. October 31st, 2005CSICS Presentation9 Circuit Description: Decision Selective Feedback ECL Master Slave Flip flop

10. October 31st, 2005CSICS Presentation10 Circuit Description: Decision Selective Feedback ECL Selector

11. October 31st, 2005CSICS Presentation11 Circuit Description: Decision Selective Feedback Design of critical path using sum of OCTC

12. October 31st, 2005CSICS Presentation12 Circuit Description: Decision Selective Feedback Design of critical path using sum of OCTC 1. Minimize transistor time constants, by biasing at peak f t / f max collector current density

13. October 31st, 2005CSICS Presentation13 Circuit Description: Decision Selective Feedback Design of critical path using sum of OCTC 1. Minimize transistor time constants, by biasing at peak f t / f max collector current density 2. Minimize the interconnect capacitance to tail current ratio through layout and by increasing collector current

14. October 31st, 2005CSICS Presentation14 Circuit Description: Decision Selective Feedback Design of critical path using sum of OCTC 1. Minimize transistor time constants, by biasing at peak f t / f max collector current density 2. Minimize the interconnect capacitance to tail current ratio through layout and by increasing collector current 3. Minimize voltage swing (or load resistor)

15. October 31st, 2005CSICS Presentation15 DIE Photo 1. Broadband front end 2. Slicers 3. Decision selective feedback 4. Output driver 5. Clock Buffer 1 2 3 5 4

16. October 31st, 2005CSICS Presentation16 Measurements: BERT 20-ft SMA cable ■ 20-ft SMA cable ►  dB of attenuation at 5GHz ■ Measurement Goal: Highest frequency BERT test possible at the University of Toronto 20-ft SMA cable S 21

17. October 31st, 2005CSICS Presentation17 Measurements: BERT 10-Gbps 20-ft SMA cable Input Eye – 20-ft SMA CableEqualized Output Eye Jitter pp = 10.22ps; SNR = 13.13 Rise time = 18.7ps; V pp = 290mV

18. October 31st, 2005CSICS Presentation18 Measurements: 40-Gbps Large Signal Measurements

19. October 31st, 2005CSICS Presentation19 Measurements: 40-Gbps Large Signal Measurements ■ 9-ft SMA cable ►  dB of attenuation at 20GHz ■ Measurement Goal: Prove error free functionality at 40-Gbps 9-ft SMA cable S 21

20. October 31st, 2005CSICS Presentation20 Measurements: 40-Gbps Large Signal Measurements Input Eye – 9-ft SMA CableEqualized Output Eye Jitter pp = 5.11ps; SNR = 9.1 Rise time = 13.67ps; V pp = 320mV

21. October 31st, 2005CSICS Presentation21 Measurements: 40-Gbps Large Signal Measurements ■ Manually verified 508-bit sequence (4x2 7 -1 PRBS) via the waveform capture feature of oscilloscope ■ Errors in middle waveform indicated by arrows Reference DFE output  = 0 DFE output  ≠ 0

22. October 31st, 2005CSICS Presentation22 Measurement Summary TechnologyJazz Semiconductor 0.18  m SiGe BiCMOS Supply Voltage3.3V Data Rate40-Gbps Power Dissipation760mW Broadband front end95mW Slicers160mW Decision Selective Feedback225mW Output Driver95mW Clock Path185mW Return Loss< -10 dB up to 40 GHz Output Peak-to-Peak Jitter5.11ps @ 40 Gbps Rise/Fall time13.67/6 ps @ 40 Gbps Output Swing324mV @ 40 Gbps Chip Size1.5mm 2

23. October 31st, 2005CSICS Presentation23 Conclusion ■ Design ► 1-Tap look-ahead architecture ► Broadband up to 40-Gbps ► Broadband, linear, low noise input stage ■ Performance ► Demonstrated equalization of a 20-ft SMA cable at 10 Gbps ● BER of less than 10 -12 ► At 40-Gbps, the DFE equalized a 9-ft SMA cable with error free operation ■ This is the first 40-Gbps DFE in silicon

24. October 31st, 2005CSICS Presentation24 Acknowledgements ■ NIT, OIT, CFI for test equipment ■ NSERC, Gennum and Micronet for financial support ■ Jazz Semiconductor for technology access ■ CAD tools by the Canadian MicroelectronicsCorportation (CMC)

25. October 31st, 2005CSICS Presentation25 Questions?

26. October 31st, 2005CSICS Presentation26 Backup

27. October 31st, 2005CSICS Presentation27 Fabrication ■ Break out circuit of the broadband front end ■ Linear measurements

28. October 31st, 2005CSICS Presentation28 Measurements: S-Parameter Return Loss on High Frequency Ports Broadband Front End S 21

29. October 31st, 2005CSICS Presentation29 Measurements: Broadband Characterization

30. October 31st, 2005CSICS Presentation30 Measurements: Broadband Characterization

31. October 31st, 2005CSICS Presentation31 Measurements: BERT

32. October 31st, 2005CSICS Presentation32 Measurements: 40-Gbps Large Signal Measurements