BTeV Hybrid Pixels David Christian Fermilab July 10, 2006

Context BTeV was possible because of two “enabling technologies.” 1.A silicon pixel detector with very high segmentation and very fast, zero suppressed, readout. 2.A vertex trigger (using pixel hits) capable of accepting data from more than 15 million events per second, selecting events containing measurable b decays, and rejecting backgrounds.

Advantages of hybrid silicon pixel detectors Excellent spatial resolution –High stopping power of silicon: Most ionization is contained within a few microns of a track. A minimum ionizing particle creates 80 e/h pairs per micron of track length. –Low noise electronics: Small sensor pixel and bump bonding means very small input capacitance. Separate development of sensor and readout chip allows each to be optimized.

Topic 1: Major milestones in module R&D Readout ChipSensorBumpsAdvances FPIX0 – 1997 (64x16) 0.8  CMOS ATLAS ST-1 (p-stop & p-spray) CiS & Seiko Indium (Boeing) 1998 <100 e - noise  < 9  with 2-3 ADC bits FPIX1 – 1999 (160x18) 0.5  CMOS BTeV/CMS proto (p-stop) Sintef Indium (AIT) & Solder (MCNC) 2000 – 2001 Readout speed (Column-parallel architecture) FPIX2 – 2002 (128x22) 0.25  CMOS BTeV proto (moderated p-spray) Tesla Indium (AIT) & Solder (VTT) 2002 – 2004 Radiation Hard Higher speed (~30 ns/hit), ease of use (DAC’s & I/O) multichip modules beam tested

Status as of February 2005 Sensor module R&D complete –Licensed use of “moderated p-spray” n-in-n technology developed for ATLAS Chip development near completion Two failures must be corrected: –Readout hangs when multiple pixels are hit in ~200ps interval as BCO number is incrementing (design change is done). –Amplifier oscillates after irradiation with large leakage current. Other readout/mechanical design well advanced (but BTeV-specific).

The last 16 months Proposal to finish development of BTeV pixels in the context of ILC detector R&D was approved in May, –Construction of a pixel telescope for the forward arm of PHENIX is a part of this. –Final readout chip (FPIX2.1) has been tested. Both faults have been corrected. –A “general purpose” HDI has been designed and fabricated.

FPIX2 at a glance Designed to be the BTeV pixel chip. 50  x 400  pixels (like ATLAS). 22 columns x 128 rows. –Designed to tile chips in one line with 600  long pixels between chips; not designed to tile two lines of chip on one sensor module. High speed, zero suppressed readout. –Can be ~30ns/hit. –All chips read out in parallel on point-to-point links. NO TRIGGER. Easy to use. –One bias voltage (+2.5V) –All LVDS I/O – No other ASIC’s required.

FPIX2 Block Diagram Pixel Unit Cells (22 columns of 128 rows each) End-of-Column logic (22 copies) Core Logic Core DAC’s Programmable Registers Programming Interface Steering Logic Word Serializer Next Word Block Clock Control Logic Input/OutputHigh Speed Output Data Output Clock BCO Clock Data Output Interface Fabricated by TSMC (through MOSIS). Only bias voltages required are 2.5V & ground. All I/O is LVDS.

FlashLatchto Binary Encoder Thermometer Thresholds (Vth1-Vth7) Sensor Command Interpreter idle reset output listen HFastOR RFastORThrottle4 pairs of Command Lines Kill ADC Row Address Read Clock Read Reset Token In Token Reset Token Out Threshold (Vth0)Vref Resets Bus Controller - + Vdda Test Inject Vfb2 Pixel Unit Cell

Pixel Cells (four 50 x 400 mm cells) 12 µm bump pads Preamp2 nd stage +disc ADC Kill/ inject ADC encoder Digital interface (Top metal layer not shown)

Pixel Module NOT TO SCALE FPIX2 Silicon Sensor HDI Wire bonds Bump bonds 250 µm 50 µm 200 µm 210 µm

Detector building blocks Pixel size = 50 microns x 400 microns Readout chip services 22 columns of 128 rows of pixels Module = Single row of readout chips bonded to a sensor (4,5,6, or 8 readout chips) Active area of 8x module = 73.6mm x 6.4mm; current HDI is 104.5mm x 11.1mm.

A possible building block 36.8 mm