Component Design By the end of the course each student will design and test a MIPS processor Datapath components will be designed and tested in the next.

Slides:

Advertisements

Similar presentations

Stimulus and Response. Simple Stimulus Verifying the Output Self-Checking Testbenches Complex Stimulus Complex Response Predicting the Output.

Advertisements

Chapter 15:Introduction to Verilog Testbenches Objectives In this section,you will learn about designing a testbench: Creating clocks Including files Strategic.

Counters Discussion D8.3.

1 COMP541 More on State Machines and Video Scanout Montek Singh Feb 13, 2007.

VHDL Lecture 1 Megan Peck EECS 443 Spring 08.

Verilog in transistor level using Microwind

Simulation executable (simv)

The Verilog Hardware Description Language

Synchronous Sequential Logic

EE 361 Fall 2003University of Hawaii1 Hardware Design Tips EE 361 University of Hawaii.

Multiplication and Division

Verilog Modules for Common Digital Functions

Table 7.1 Verilog Operators.

Verilog Intro: Part 1.

COE 405 Design and Synthesis of DataPath Controllers Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals.

CSE 201 Computer Logic Design * * * * * * * Verilog Modeling

Verilog. 2 Behavioral Description initial:  is executed once at the beginning. always:  is repeated until the end of simulation.

1 Brief Introduction to Verilog Weiping Shi. 2 What is Verilog? It is a hardware description language Originally designed to model and verify a design.

//HDL Example 6-1 // //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.

1 Lecture 1: Verilog HDL Introduction. 2 What is Verilog HDL? Verilog Hardware Description Language(HDL)? –A high-level computer language can model, represent.

OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.

1 Brief Introduction to Verilog Weiping Shi. 2 What is Verilog? It is a hardware description language Allows designers to quickly create and debug large.

Ring Counter Discussion 11.3 Example 32.

Arbitrary Waveform Discussion 12.2 Example 34. Recall Divide-by-8 Counter Use q2, q1, q0 as inputs to a combinational circuit to produce an arbitrary.

Counters Discussion 12.1 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

2-to-1 Multiplexer: if Statement Discussion D7.1 Example 4.

A/D Converter Datapaths Discussion D8.4. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit:

ELEN 468 Advanced Logic Design

Advanced Verilog EECS 270 v10/23/06.

Registers and Shift Registers Discussion D8.2. D Flip-Flop X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive.

Generic Multiplexers: Parameters Discussion D7.5 Example 8.

D Flip-Flops in Verilog Discussion 10.3 Example 27.

Quad 2-to-1 Multiplexer Discussion D7.4 Example 7.

9/15/09 - L25 Registers & Load Enable Copyright Joanne DeGroat, ECE, OSU1 Registers & Load Enable.

Engineering 100 Section 250 Combinational Logic -- Examples 9/13/2010.

Overview Logistics Last lecture Today HW5 due today

Sequential Logic in Verilog

Verilog Digital System Design Z. Navabi, 2006

Verilog Intro: Part 2. Procedural Blocks There are two types of procedural blocks in Verilog. – initial for single-pass behavior: initial blocks execute.

Week Four Design & Simulation Example slides. Agenda Review the tiny example (Minako “logic”)from last week – look at the detailed static timing report.

Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL) A hardware description language is a language or means used to describe or model a digital.

ECE 551 Digital System Design & Synthesis Fall 2011 Midterm Exam Overview.

CS 61C L4.2.2 Verilog II (1) K. Meinz, Summer 2004 © UCB CS61C : Machine Structures Lecture Verilog II Kurt Meinz inst.eecs.berkeley.edu/~cs61c.

Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Ders 8: FSM Gerçekleme ve.

Slide 1 6. VHDL/Verilog Behavioral Description. Slide 2 Verilog for Synthesis: Behavioral description Instead of instantiating components, describe them.

1 CSE-308 Digital System Design (DSD) N-W.F.P. University of Engineering & Technology, Peshawar.

Final Project. System Overview Description of Inputs reset: When LOW, a power on reset is performed. mode: When LOW, NORMal mode selected When HIGH,

Chap. 4 Modules and Ports. 2 Modules and Ports Modules Ports Hierarchical Names Summary.

1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,

Finite State Machine (FSM) Nattha Jindapetch December 2008.

1 Arithmetic, ALUs Lecture 9 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 4: Testing, Dataflow Modeling Spring 2009.

 A test bench is an HDL program used for applying stimulus to an HDL design in order to test it and observe its response during simulation.  In addition.

Multiplexers Section Topics Multiplexers – Definition – Examples – Verilog Modeling.

Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Chapter 11: System Design.

1 Lecture 1: Verilog HDL Introduction. 2 What is Verilog HDL? Verilog Hardware Description Language(HDL)? –A high-level computer language can model, represent.

Exp#7 Finite State Machine Design in Verilog COE203 Digital Logic Laboratory Dr. Ahmad Almulhem KFUPM Spring 2009.

1 A hardware description language is a computer language that is used to describe hardware. Two HDLs are widely used Verilog HDL VHDL (Very High Speed.

Overview Logistics Last lecture Today HW5 due today

TODAY’S OUTLINE Verilog Codings Concurrent and Sequential If-else

Verilog Introduction Fall

TODAY’S OUTLINE Testbench Circuit Verilog Operators

Hardware Description Languages

Lecture 9. MIPS Processor Design – Decoding and Execution

Register-Transfer Level Components in Verilog

The Verilog Hardware Description Language

CS 153 Logic Design Lab Professor Ian G. Harris

The Verilog Hardware Description Language

Presentation transcript:

Component Design By the end of the course each student will design and test a MIPS processor Datapath components will be designed and tested in the next few labs (registers, multiplexers, alu’s, etc.) Controller will be designed as a state machine Controller and datapath will be combined and it will be used to run a machine program

Design and Test Strategy Reference Model Design Compare Stimulus Generation Each design will be tested by comparison to a reference model Reference model should perform exactly as the real design Both reference and design receive the same input

Reference Model Reference model is behavioral, design is structural A behavioral design is easier to create and easier to assume correct Difficulties A bug in either the reference model or the design will be detected The reference model must be debugged before the design The reference model may not be timing-accurate

Reference Model Example module MUX_behav (f, sel, b, c); output reg f; input sel, a, b; (sel or a or b) begin if (sel == 1) f = b; else f = a; end endmodule module MUX_struct (f, a, b, sel); outputf; inputa, b, sel; and #5g1 (f1, a, nsel), g2 (f2, b, sel); or #5g3 (f, f1, f2); notg4 (nsel, sel); endmodule Behavioral Reference ModelStructural Design

Testbench with Reference Model module mux_comp (mismatch, in1, in2, sel) input in1, in2, sel; output mismatch; wire out1, out2; MUX_behav m1 (out1, in1, in2, sel); MUX_struct m2 (out2, in1, in2, sel); xor x1 (mismatch, out1, out2); endmodule module mux_tb (mismatch) wire in1, in2, sel; output mismatch; mux_comp m1 (mismatch, in1, in2, sel); always … endmodule Error is detected by observing the mismatch signal

Reference Model for a Design with Timing module mult_behav (prod, in1, in2) input [7:0] in1, in2; output [15:0] prod; res = in1 * in2; endmodule module mult_struct (prod, in1, in2, clk) input [7:0] in1, in2; input clk; output [15:0] prod; // shift-add algorithm endmodule Design is timing-accurate, reference model is not Need to choose the sample points

A Sample Clock module mult_comp (in1, in2, clk, sclk) // declare inputs, outputs, wires mult_behav m1 (out1, in1, in2); mult_struct m2 (out2, in1, in2, clk); always (sclk) if (out1 != out2) $display(“error); endmodule module mult_tb wire in1, in2, clk, sclk; mult_comp m1 (in1, in2, clk, sclk); initial clk = 0; sclk = 0; always #5 sclk = ~sclk; always (sclk) #1 clk = ~clk; always … endmodule Signals must settle just before the clock Sample clock rises just before regular clock