Feb. 26, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 12: State Elements, Registers, and Memory * Jeremy R. Johnson Mon. Feb. 26, 2001 *This lecture was derived from material in the text (Appendix B). All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).

Feb. 26, 2001Systems Architecture I2 Introduction Objective: Review sequential logic and use of a clock. To learn how to use flip flops to build register files, and latches to build memory. Topics –Sequential logic (elements with state) and timing (edge triggered) Latches and flip flops Registers –Memory SRAM DRAM

Feb. 26, 2001Systems Architecture I3 Timing Clocks used in synchronous logic – when should an element that contains state be updated? –All state elements must have the clock signal as an input Edge-triggered timing –All state elements are updated on the same clock edge cycle time rising edge falling edge

Feb. 26, 2001Systems Architecture I4 Edge Triggered Timing State updated at clock edge read contents of some state elements, send values through some combinational logic write results to one or more state elements Clock must have sufficiently long period for combinational logic to stabilize.

Feb. 26, 2001Systems Architecture I5 Edge Triggered Timing Allows a state element to be used as both an input and an output

Feb. 26, 2001Systems Architecture I6 S-R (set-reset) Latch Unclocked memory element The outputs Q and Qb represent the value of the stored element and its complement. When neither S or R is asserted the cross-coupled nor gates serve as inverters and store the previous values of Q and Qb If S is asserted Q will be asserted and Qb will be deasserted If R is asserted Qb will be asserted and Q will be deasserted Asserting both S and R can lead to incorrect behavior

Feb. 26, 2001Systems Architecture I7 D Latch Clocked memory unit (change of state triggered by clock) State is changed whenever inputs change and clock is asserted Transparent

Feb. 26, 2001Systems Architecture I8 D Flip-Flop Clocked memory unit (change of state triggered by clock) State is changed only on the clock edge (can be designed to use either the rising or falling edge) Since we use edge-triggered timing, flip-flops are used Not transparent Uses two D latches (master & slave)

Feb. 26, 2001Systems Architecture I9 Behavioral Model for D Flip-Flop Library IEEE; use IEEE.std_logic_1164.all; entity dff is port(D, Clk : in std_logic; Q, Qb : out std_logic); end dff; architecture behavorial of dff is begin output: process begin wait until (Clk’event and Clk = ‘0’); Q <= D after 5 ns; Qb <= not D after 5 ns; end process output; end behavorial;

Feb. 26, 2001Systems Architecture I10 Components for Simple Implementation Functional Units needed for each instruction

Feb. 26, 2001Systems Architecture I11 Register File A set of registers that can be read/written by supplying a register number to be accessed. Built using a decoder for each read and write port, and an array of D flip-flops. For the MIPS processor, the register file has two read ports and one write port. A write flag is used to indicate that the state should change, and a clock is needed to determine when to change state.

Feb. 26, 2001Systems Architecture I12 Implementation of Read Ports

Feb. 26, 2001Systems Architecture I13 Implementation of Write Ports

Feb. 26, 2001Systems Architecture I14 Memory Registers and register files provide the basic building blocks for small memories. Larger memories are built from SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories) SRAM –5 to 25 ns access time –largest SRAMs have over 4 Million bits –4 to 6 transistors per bit –value stored in cell kept on a pair of inverting gates and can be kept indefinitely DRAM –60 to 110 ns access time –1 transistor per bit –charge stored in capacitor, and needs periodic refreshing

Feb. 26, 2001Systems Architecture I15 SRAM Specification given in terms of number of addressable locations (height) and width of each location Example –256K  1 (18 address bits and 1 bit wide) –32K  8 (15 address bits and 8 bits wide) Control lines –chip select –output enable (for read) –write enable

Feb. 26, 2001Systems Architecture I16 Three-State Buffers With an SRAM with 32K or 256K address bits, using a multiplexor to select the output is out of the question. Large memories are implemented using a shared output line, called a bit line, which multiple cells in the memory array can assert. To allow multiple sources to drive a single line, a three- state buffer is used. –Output is asserted or deasserted if output enable is asserted –Otherwise is in a high-impedance state which allows another three-state buffer that is enabled to determine the output

Feb. 26, 2001Systems Architecture I17 Structure of a 4  2 SRAM

Feb. 26, 2001Systems Architecture I18 Two-Level Decoding A two-level decoding scheme is used (avoids large decoder or multiplexor)

Feb. 26, 2001Systems Architecture I19 DRAM Uses two-level decoder Row access followed by column access –Row access chooses an entire row which is copied to a to a set of latches (written back for refresh) –Column access selects from the column latches –One set of pins used –Row Access Strobe (RAS) and Column Access Strobe (CAS) signal DRAM that either a row or column address is being supplied

Feb. 26, 2001Systems Architecture I20 Recent Developments Synchronous SRAM and DRAM –provide ability to transfer a burst of data from a series of sequential addresses within an array or row. –Initial address and burst length provided –A clock is used to transfer successive bits in burst In a DRAM access all but one element of a row is thrown out. Page mode or static-column mode allow the column address to change with a fixed row address (difference is whether CAS must be reasserted) EDO RAM (Extended Data Out) is an example which provides access times at 25ns.

Feb. 26, 2001Systems Architecture I21 Behavioral Model for Memory library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity memory is port(address, write_data : in std_logic_vector(31 downto 0); MemWrite, MemRead : in std_logic; read_data : out std_logic_vector(31 downto 0)); end memory;

Feb. 26, 2001Systems Architecture I22 Behavioral Model for Memory architecture behavorial of memory is type mem_array is array(0 to 7) of std_logic_vector (31 downto 0); begin mem_process: process(address, write_data) variable data_mem : mem_array := ( to_stdlogicvector(X” ”), --- initialize data memory to_stdlogicvector(X” ”), to_stdlogicvector(X” ”)); variable adddr : integer;

Feb. 26, 2001Systems Architecture I23 Behavioral Model of Memory begin addr := to_integer(address (2 downto 0)); if MemWrite = ‘1’ then data_mem(addr) := write_data; elsif MemRead = ‘1’ then read_data := data_mem(addr) after 10 ns; end if; end process mem_process; end behavorial;