SCIPP R&D on the International Linear Collider Detector DOE Site Visit June 28, 2005 Presenter: Bruce Schumm.

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Presentation transcript:

SCIPP R&D on the International Linear Collider Detector DOE Site Visit June 28, 2005 Presenter: Bruce Schumm

Activity is increasing, with studies now on four fronts:  Physics and machine studies for e - e - running  Detector resolution standards from physics simulation  Hardware proof-of-principle of low-mass silicon tracking  Reconstruction capabilities of all-silicon tracking Current involvements (all very much part time) 3 senior physicists, 2 post-docs, 2 graduate students, 4 undergraduate thesis students, 1 Engineer, 1 technical staff, one bored housewife.

Detector Resolution Standards from Selectron Production Participants: Senior Physicist Bruce Schumm Undergraduate Thesis Students Troy Lau *, Joseph Rose, Matthew Vegas, Eric Wallace Community Member (on hold before Grad School) Ayelet Lorberbaum * Recipient of two Undergraduate Research Awards; grad school at U. Michigan this fall.

Original Motivation To explore the effects of limited detector resolution on our ability to measure SUSY parameters in the forward (|cos(  )| >.8) region. SiD Tracker

selectrons LSP SPS 1 Spectroscopy: At E cm = 1Tev, selectrons and neutralino are light. Beam/Brehm: √s min =1 √s max =1000  =.29 s z =.11 (mm)

SPS1A at 1 TeV Selectrons vs. cos(  ) Electrons vs. cos(  ) Roughly ½ of statistics above |cos(  )| of 0.8, but…

sample electron energy distribution M selectron = (SPS1A) Lower Endpoint Upper Endpoint Electron energy distribution with beam/bremm/ISR (.16%). No detector effects or beam energy spread.

The spectrum is weighted towards higher energy at high |cos(  )|, so there’s more information in the forward region than one might expect.

Determine the selectron mass accuracy in both the central (0 < |cos  | < 1) and full (0 < |cos  | < 1) region

Detailed Simulation of SiD Tracking System (and SiD variants) Participants: Senior Physicist Bruce Schumm Graduate Students Christian Flacco, Luke Winstrom, Michael Young * * Supported primarily through department (TA) funds; work deemed important enough that SLAC is paying for ½ of his support this summer.

Two areas of work: Pulse Development Simulation Provides simulation of pulse development and amplification. Will soon be incorporated in international simulation framework (awaiting “hook” from Norman Graf at SLAC) SiD Tracking Capabilities Explore tracking performance of five-layer SiD tracker, as well as that of 8-layer variant Detailed Simulation of SiD Tracking System (and SiD variants), continued

Pulse Development Simulation Long Shaping-Time Limit: strip sees signal if and only if hole is col- lected onto strip (no electrostatic coupling to neighboring strips) Charge Deposition: Landau distribution (SSSimSide; Gerry Lynch LBNL) in ~20 independent layers through thickness of device Geometry: Variable strip pitch, sensor thickness, orientation (2 dimen- sions) and track impact parameter Lorentz Angle: 18 mrad per Tesla (holes), from measurements

Carrier Diffusion Hole diffusion distribution given by Offest t 0 reflects instantaneous expansion of hole cloud due to space-charge repulsion. Diffusion constant given by Reference: E. Belau et al., NIM 214, p253 (1983)  h = hole mobility

Electronics Simulation Detector Noise: From SPICE simulation, normalized to bench tests with GLAST electronics Analog Measurement: Employs time-over- threshold with variable clock speed; lookup table provides conversions back into analog pulse height (as for actual data) RMS Gaussian Fit Detector Resolution (units of 10  m)

Senior Physicists Alex Grillo, Bruce Schumm Post-Doctoral Fellows Jurgen Kroseberg, Gavin Nesom Technical Staff Ned Spencer*, Max Wilder * Lead Engineer Hardware Development of Long Shaping-Time  strip Readout for the Linear Collider Detector

FIFO (Leading and trailing transitions) Low Comparator Leading-Edge-Enable Domain Proposed LSTFE Back-End Architecture Clock Period  = 400 nsec Event Time 8:1 Multi- plexing (  clock = 50 ns)

Master FIFO Per 128 Channel Chip: 1 Master FIFO reads out 32 local FIFO’s Store in Master FIFO essentially complete by end of ~1ms beam spill Controller FIFO Proposed LSTFE Back-End Architecture (cont’d)