DBS A Bit-level Heuristic Packet Classification Algorithm for High Speed Network Author : Baohua Yang, Xiang Wang, Yibo Xue, Jun Li Publisher : th International Conference on Parallel and Distributed Systems Presenter: Tung-yin Chi Date: 2015/3/11 Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

Introduction (1/2) In this paper, we propose a novel packet classification algorithm named DBS (Discrete Bit Selection) which takes a bit level heuristic design to partition the rule set effectively. To evaluate the performance of our algorithm, DBS is deployed on a popular multi-core Network Processor platform, compared with two existing well-known algorithms. National Cheng Kung University CSIE Computer & Internet Architecture Lab 2

Introduction (2/2) Experimental results show that DBS achieves 300% higher throughput than HiCuts and HSM, while the memory requirement is reduced to about 10% averagely. DBS works well especially with large rule set (10K),which trends a good scalability. National Cheng Kung University CSIE Computer & Internet Architecture Lab 3

DBS Algorithm DBS is designed basing on two principles (i) Use bitlevel heuristics to split rules efficiently (ii) Adopt adaptive flat data structures to guarantee fast searching with low memory requirement. National Cheng Kung University CSIE Computer & Internet Architecture Lab 4

Data structure E-bits Selected bits to split the rule set Mask vector Use mask to get the value of E-bits EX: if bit 0 and bit 3 are selected as E-bits, the mask vector = 1001 National Cheng Kung University CSIE Computer & Internet Architecture Lab 5

Preparation phase Mask Vector Generation Select E-bits and generate mask Lookup Table Construction Use the trie created by using mask vector to construct the table. National Cheng Kung University CSIE Computer & Internet Architecture Lab 6

Preparation phase Mask = 0101 National Cheng Kung University CSIE Computer & Internet Architecture Lab 7

Classification Phase National Cheng Kung University CSIE Computer & Internet Architecture Lab 8

Test bed(Software Simulation) PC 2.0GHz dual-core 4GB DDRII memory All programs are C-code and complied with - O2 option under Ubuntu 8.04 Linux system. National Cheng Kung University CSIE Computer & Internet Architecture Lab 9

Test bed Cavium OCTEON 5860 multi-core platform 16 MHz 2MB L2 cache 4 GB DDR2 SDRAM There are two programming modes provided by Cavium SDK Linux mode (with a Linux OS) Simple Executive mode(without OS supporting).We program codes at the The codes are programed at Simple Executive mode for fast packet processing. National Cheng Kung University CSIE Computer & Internet Architecture Lab 10

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 11

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 12

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 13

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 14

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 15

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 16

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 17

Performance Results National Cheng Kung University CSIE Computer & Internet Architecture Lab 18