1. 1 Hybrid cache architecture for high-speed packet processing Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C. Authors: Z. Liu, K. Zheng and B. Liu Publisher: Computers & Digital Techniques, IET; Volume 1, Issue 2, March 2007 Page(s):105 – 112 Present: Fang-Chen, Kuo ( 郭芳辰 ) Date: December, 18, 2007

2. 2 Outline Split-Control Cache App-Cache Flow-Cache Memory Scheduler Performance Evaluation

3. 3 Cache What? Cache data structure for processing packet Flow-relevant data structure Shared among packets from the same flow Spatial Locality Application-relevant data structure Access for every incoming packet Ex: Table for routing Temporal Locality => Control Data

4. 4 Split-Control Cache For which architecture ? For Network Processor Based Architecture (next page) Flow-Cache and App-Cache Why Split ? Spatial Locality of Flow-relevant Structure Space Requirement

5. 5 Base NP Architecture (AMCC nP3700) Notice that the packet classification is done by Coprocessor.

6. 6 App-Cache The app-cache has the same organization with conventional caches.

7. 7 Split-Control Cache Architecture

8. 8 Pipelined execution of flow-cache

9. 9 Flow-Cache Architecture

10. 10 Memory Scheduler Priority Sequence: Read > Write App-Cache are needed immediately for packet processing. App. Read > Flow. Read App. Data are seldom modified by packet processing, so Flow. Write > App. Write Hardware supported memory scheduling