CHAPTER 6: The Little Man Computer The Architecture of Computer Hardware and Systems Software: An Information Technology Approach 3rd Edition, Irv Englander John Wiley and Sons 2003 Linda Senne, Bentley College Wilson Wong, Bentley College

The Little Man Computer Chapter 6 Little Man Computer

Mailboxes: Address vs. Content Addresses are consecutive Content may be Data or Instructions Address Content Chapter 6 Little Man Computer

Content: Instructions Op code Operation code Arbitrary mnemonic Operand Object to be manipulated Data or Address of data Address Content Op code Operand Chapter 6 Little Man Computer

Magic! Load program into memory Put data into In Basket Chapter 6 Little Man Computer

Assembly Language Specific to a CPU 1 to 1 correspondence between assembly language instruction and binary (machine) language instruction Mnemonics (short character sequence) represent instructions Used when programmer needs precise control over hardware, e.g., device drivers Chapter 6 Little Man Computer

Instruction Set Arithmetic 1xx ADD 2xx SUB Data Movement 3xx STORE 5xx LOAD Input/Output 901 INPUT 902 Output Machine Control (coffee break) 000 STOP COB Chapter 6 Little Man Computer

Input/Output Move data between calculator and in/out baskets Content Op Code Operand (address) IN (input) 9 01 OUT (output) 02 Chapter 6 Little Man Computer

LMC Input/Output IN OUT Chapter 6 Little Man Computer

Internal Data Movement Between mailbox and calculator Content Op Code Operand (address) STO (store) 3 xx LDA (load) 5 Chapter 6 Little Man Computer

LMC Internal Data LDA STO Chapter 6 Little Man Computer

Data storage location Physically identical to instruction mailbox Not located in instruction sequence Identified by DAT mnemonic Chapter 6 Little Man Computer

Arithmetic Instructions Read mailbox Perform operation in the calculator Content Op Code Operand (address) ADD 1 xx SUB 2 Chapter 6 Little Man Computer

LMC Arithmetic Instructions ADD SUB Chapter 6 Little Man Computer

Simple Program: Add 2 Numbers Assume data is stored in mailboxes with addresses >90 Write instructions Input a # Store the # Add Output the number Chapter 6 Little Man Computer

Program to Add 2 Numbers: Using Mnemonics Mailbox Mnemonic Instruction Description 00 IN ;input 1st Number 01 STO 99 ;store data 02 ;input 2nd Number 03 ADD 99 ;add 1st # to 2nd # 04 OUT ;output result 05 COB ;stop 99 DAT 00 ;data Chapter 6 Little Man Computer

Program to Add 2 Numbers Mailbox Code Instruction Description 00 901 ;input 1st Number 01 399 ;store data 02 ;input 2nd Number 03 199 ;add 1st # to 2nd # 04 902 ;output result 05 000 ;stop 99 ;data Chapter 6 Little Man Computer

Program Control Branching (executing an instruction out of sequence) Changes the address in the counter Halt Content Op Code Operand (address) BR (Jump) 6 xx BRZ (Branch on 0) 7 BRP (Branch on +) 8 COB (stop) (ignore) Chapter 6 Little Man Computer

Instruction Set Arithmetic 1xx ADD 2xx SUB Data Movement 3xx STORE 5xx LOAD BR 6xx JUMP BRZ 7xx BRANC ON 0 BRP 8xx BRANCH ON + Input/Output 901 INPUT 902 OUTPUT Machine Control (coffee break) 000 HALT COB Chapter 6 Little Man Computer

Find Positive Difference of 2 Numbers 00 IN 901 01 STO 10 310 02 03 STO 11 311 04 SUB 10 210 05 BRP 08 808 ;test 06 LDA 10 510 ;if negative, reverse order 07 SUB 11 211 08 OUT 902 ;print result and 09 COB 000 ;stop 10 DAT 00 ;used for data 11 Chapter 6 Little Man Computer

Instruction Cycle Fetch: Little Man finds out what instruction he is to execute Execute: Little Man performs the work. Chapter 6 Little Man Computer

Fetch Portion of Fetch and Execute Cycle 1. Little Man reads the address from the location counter 2. He walks over to the mailbox that corresponds to the location counter Chapter 6 Little Man Computer

Fetch, cont. 3. And reads the number on the slip of paper (he puts the slip back in case he needs to read it again later) Chapter 6 Little Man Computer

Execute Portion 1. The Little Man goes to the mailbox address specified in the instruction he just fetched. 2. He reads the number in that mailbox (he remembers to replace it in case he needs it later). Chapter 6 Little Man Computer

Execute, cont. 3. He walks over to the calculator and punches the number in. 4. He walks over to the location counter and clicks it, which gets him ready to fetch the next instruction. Chapter 6 Little Man Computer

von Neumann Architecture (1945) Stored program concept Memory is addressed linearly Memory is addressed without regard to content Chapter 6 Little Man Computer

Buses There are a number of possible interconnection systems Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP) Chapter 6 Little Man Computer

What is a Bus? A communication pathway connecting two or more devices Usually broadcast Often grouped A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown Chapter 6 Little Man Computer

Data Bus Carries data Width is a key determinant of performance Remember that there is no difference between “data” and “instruction” at this level Width is a key determinant of performance 8, 16, 32, 64 bit Chapter 6 Little Man Computer

Address bus Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system e.g. 8080 has 16 bit address bus giving 64k address space Chapter 6 Little Man Computer

Control Bus Control and timing information Memory read/write signal Interrupt request Clock signals Chapter 6 Little Man Computer

Bus Interconnection Scheme Chapter 6 Little Man Computer

Big and Yellow? What do buses look like? Parallel lines on circuit boards Ribbon cables Strip connectors on mother boards e.g. PCI Sets of wires Chapter 6 Little Man Computer

Physical Realization of Bus Architecture Chapter 6 Little Man Computer

Single Bus Problems Lots of devices on one bus leads to: Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems Chapter 6 Little Man Computer

Traditional (ISA) (with cache) Chapter 6 Little Man Computer

High Performance Bus Chapter 6 Little Man Computer

Bus Types Dedicated Multiplexed Separate data & address lines Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages More complex control Ultimate performance Chapter 6 Little Man Computer

Bus Arbitration More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed Chapter 6 Little Man Computer

Centralised or Distributed Arbitration Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate Distributed Each module may claim the bus Control logic on all modules Chapter 6 Little Man Computer

Timing Co-ordination of events on bus Synchronous Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event Chapter 6 Little Man Computer

Synchronous Timing Diagram Chapter 6 Little Man Computer

Asynchronous Timing – Read Diagram Chapter 6 Little Man Computer

Asynchronous Timing – Write Diagram Chapter 6 Little Man Computer

PCI Bus Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines Chapter 6 Little Man Computer

PCI Bus Lines (required) Systems lines Including clock and reset Address & Data 32 time mux lines for address/data Interrupt & validate lines Interface Control Arbitration Not shared Direct connection to PCI bus arbiter Error lines Chapter 6 Little Man Computer

PCI Bus Lines (Optional) Interrupt lines Not shared Cache support 64-bit Bus Extension Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transfer JTAG/Boundary Scan For testing procedures Chapter 6 Little Man Computer

PCI Commands Transaction between initiator (master) and target Master claims bus Determine type of transaction e.g. I/O read/write Address phase One or more data phases Chapter 6 Little Man Computer

PCI Read Timing Diagram Chapter 6 Little Man Computer

PCI Bus Arbiter Chapter 6 Little Man Computer

PCI Bus Arbitration Chapter 6 Little Man Computer

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