Multiplexers and Demultiplexers

Slides:



Advertisements
Similar presentations
Modular Combinational Logic
Advertisements

Multiplexer as a Universal Function Generator Lecture L6.7 Section 6.2.
Decoders/DeMUXs CS370 – Spring Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of.
DIGITAL SYSTEMS TCE OTHER COMBINATIONAL LOGIC CIRCUITS WEEK 7 AND WEEK 8 (LECTURE 3 OF 3) MULTIPLEXERS DEMULTIPLEXERS.
CS 140 Lecture 13 Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego 1.
Chapter 3 Continued Logic Gates Logic Chips Combinational Logic Timing Sequential Logic Flip Flops Registers Memory State Machines.
Multiplexer as a Universal Function Generator
Combinational Logic1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Hamming Code, K-maps-Multiplexer Midterm 1 Revision
ECE 301 – Digital Electronics Multiplexers and Demultiplexers (Lecture #12)
Multiplexer MUX. 2 Multiplexer Multiplexer (Selector)  2 n data inputs,  n control inputs,  1 output  Used to connect 2 n points to a single point.
4-bit adder, multiplexer, timing diagrams, propagation delays
Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Building Functions.
ECE2030 Introduction to Computer Engineering Lecture 10: Building Blocks for Combinational Logic (1) Timing Diagram, Mux/DeMux Prof. Hsien-Hsin Sean Lee.
Decoders and Multiplexers Prof. Sin-Min Lee Department of Computer Science San Jose State University.
Learning Outcome By the end of this chapter, students are expected to understand a few elementary components in digital system Decoder Multiplexer Demultiplexer.
Combinational Logic Design
Combinational Logic Chapter 4.
Combinational Circuit – Arithmetic Circuit
1 Digital Logic Design Week 7 Decoders, encoders and multiplexers.
WEEK #9 FUNCTIONS OF COMBINATIONAL LOGIC (DECODERS & MUX EXPANSION)
1 Lecture 9 Demultiplexers Programmable Logic Devices  Programmable logic array (PLA)  Programmable array logic (PAL)
Digital Electronics Lecture 6 Combinational Logic Circuit Design.
9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.
1 CS151: Digital Design Chapters 4, 5 Review. CS Question 1 Design a combinational circuit for a Roller-Coaster ride in an amusement park. The design.
1 Combinational Logic Design Digital Computer Logic Kashif Bashir
Mux 2.1 Multiplexers and De-Multiplexers 2: ©Paul Godin Updated November 2007.
Logical Circuit Design Week 6,7: Logic Design of Combinational Circuits Mentor Hamiti, MSc Office ,
Kuliah Rangkaian Digital Kuliah 6: Blok Pembangun Logika Kombinasional Teknik Komputer Universitas Gunadarma.
Multiplexers and Demultiplexers, and Encoders and Decoders
Multiplexers. Functional Description and Symbols.
Morgan Kaufmann Publishers
1 CSE370, Lecture 10 Lecture 10 u Logistics n HW3 due Friday (cover materials up to this lecture) n Lab3 going on this week n Midterm 1: a week from today.
ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)
CSE 140 Lecture 12 Combinational Standard Modules CK Cheng CSE Dept. UC San Diego 1.
CS 151  What does the full truth table look like? InputsOutputs D3D3 D2D2 D1D1 D0D0 A1A1 A0A0 V 0000XX
Decoders, Encoders, Multiplexers
Multiplexers and De-Multiplexers 1
CO UNIT-I. 2 Multiplexers: A multiplexer selects information from an input line and directs the information to an output line A typical multiplexer has.
IB Computer Science – Logic
EE3A1 Computer Hardware and Digital Design Worked Examples 3 Test and testability (1)
Lecture 3. Combinational Logic 2 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research.
Multiplexers and De-Multiplexers
Multiplexing and Demultiplexing
Combinational Circuit Design. Digital Circuits Combinational CircuitsSequential Circuits Output is determined by current values of inputs only. Output.
Multiplexors Decoders  Decoders are used for forming separate signals for different combination of input signals.  The multiplexer circuit is a digital.
Digital System Design Multiplexers and Demultiplexers, and Encoders and Decoders.
ECE/CS 352 Digital System Fundamentals© T. Kaminski & C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 3 -Part 2 Tom Kaminski & Charles.
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapter 4 -Part 1.
Company LOGO Edit your slogan here DKT 122/3 DIGITAL SYSTEM 1 WEEK #8 FUNCTIONS OF COMBINATIONAL LOGIC (ENCODER & DECODER, MUX & DEMUX)
MSI Combinational logic circuits
Computer Organization CSC 405 Decoders and Multiplexers.
CSE 140 Lecture 13 Combinational Standard Modules Professor CK Cheng CSE Dept. UC San Diego 1.
A multiplexer (MUX) selects one data line from two or more input lines and routes data from the selected line to the output. The particular data line that.
1 CSE370, Lecture 8 Lecture 8 u Logistics n Midterm 1 week from today in class. Closed book/closed notes n Sample midterm linked in on calendar n Review.
Chapter4: Combinational Logic Part 4 Originally By Reham S. Al-Majed Imam Muhammad Bin Saud University.
CSE 140 Lecture 12 Combinational Standard Modules CK Cheng CSE Dept. UC San Diego 1.
Multiplexer.
Gunjeet kaur Dronacharya Group of Institutions. Demultiplexers.
Multiplexer.
EKT 124 MUX AND DEMUX.
Reference: Chapter 3 Moris Mano 4th Edition
OTHER COMBINATIONAL LOGIC CIRCUITS
Circuits & Boolean Expressions
What is a Multiplexer (MUX)?
Unit5 Combinational circuit and instrumentation system.
EET107/3 DIGITAL ELECTRONICS 1
Lecture 8 Logistics Last lecture Last last lecture Today
Lecture 10 Logistics Last lecture Today
Circuits & Boolean Expressions
Presentation transcript:

Multiplexers and Demultiplexers

Design of a 2/1 Mux 2/1 mux Block Diagram Truth Table S D1 D0 O 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D0 O D1 S

Design of 2/1 Mux Continued K-Map SA 00 01 11 10 B 1 1 1 1 1 O = S’A + SB

4/1 Mux Circuit

Uses of Multiplexers Used in data communications for several computers to communicate over 1 line Used in radio to select one channel from many Used to route data within a computer Used for function generation

Function Generation using Multiplexers Given the following truth table use an 8/1 Mux to generate F Block Diagram A B C F 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 F 1 1 1 S2 S1 S0 A B C

Function Generation Continued Generate the previous F using a 4 to 1 Mux C’ F C 1 S1 S0 A B

1 to 2 Demultiplexer Truth Table Circuit S D 01 O0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 1 1 0