Computer Memory Storage Decoding Addressing 1

Memories We've Seen SIMM = Single Inline Memory Module DIMM = Dual IMM SODIMM = Small Outline DIMM RAM = Random Access Memory SDRAM = Synchronous Dynamic RAM RDRAM = Direct Rambus DRAM A type of SDRAM Rambus = The developing company ROM = Read Only Memory

Some Definitions

DRAM Comparison

Levels of the Memory Hierarchy 5 Part of The On-chip CPU Datapath ISA Registers One or more levels (Static RAM): Level 1: On-chip 16-64K Level 2: On-chip 256K-2M Level 3: On or Off-chip 1M-16M Registers Cache Level(s) Main Memory Magnetic Disc Optical Disk or Magnetic Tape Farther away from the CPU: Lower Cost/Bit Higher Capacity Increased Access Time/Latency Lower Throughput/ Bandwidth Dynamic RAM (DRAM) 256M-16G Interface: SCSI, RAID, IDE, G-300G CPU

Memory Hierarchy Comparisons 6 CPU Registers 100s Bytes <10s ns Cache K Bytes ns cents/bit Main Memory M Bytes 200ns- 500ns $ cents /bit Disk G Bytes, 10 ms (10,000,000 ns) cents/bit -5-6 Capacity Access Time Cost Tape infinite sec-min Registers Cache Memory Disk Tape Instr. Operands Blocks Pages Files Staging Xfer Unit prog./compiler 1-8 bytes cache cntl bytes OS 4K-16K bytes user/operator Mbytes faster Larger

Memory Arrays (Hierarchy) 755:035 Computer Architecture and Organization

Memory Comparisons

Non-Volatile Memories (ROM / Flash)  Floating-gate transistor Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D 9

6T SRAM Cell (6 transistors) Cell size accounts for most of array size  Reduce cell size at expense of complexity 6T SRAM Cell  Used in most commercial chips  Data stored in cross-coupled inverters Read:  Raise wordline  Read bit, bit_b (complement of bit) Write:  Drive complementary data onto bit, bit_b  Raise wordline  Bit lines overpower old data 10

1-Transistor DRAM Cell Write: Cs is charged or discharged by asserting WL and BL Read: Charge redistribution takes place between bit line and storage capacitance Voltage swing is small; typically around 250 mV 1155:035 Computer Architecture and Organization

Read-Write Memories (RAM)  Static (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential  Dynamic (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended 1255:035 Computer Architecture and Organization

Connecting Memory 55:035 Computer Architecture and Organization13 Up to 2 k addressable MDR MAR k-bit address bus n-bit data bus Control lines (, MFC, etc.) Processor Memory locations Word length =n bits WR/ MAR = Memory Address Register MDR = Memory Data Register MFC = Memory Function Complete signal

Memory Array Architecture 2 n words of 2 m bits each If n >> m, fold by 2 k into fewer rows of more columns Good regularity – easy to design Very high density if good cells are used 1555:035 Computer Architecture and Organization

Decoders n:2 n decoder consists of 2 n n-input AND gates  One needed for each row of memory  Build AND from NAND or NOR gates 1755:035 Computer Architecture and Organization

Large Decoders For n > 4, NAND gates become slow  Break large gates into multiple smaller gates 1855:035 Computer Architecture and Organization

Column Circuitry  Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing 1955:035 Computer Architecture and Organization

Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns  Must select 16 output bits from the 128 columns  Requires 16 8:1 column multiplexers 2055:035 Computer Architecture and Organization

Memory Timing: Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed 2155:035 Computer Architecture and Organization

DRAM Timing 2255:035 Computer Architecture and Organization

Serial Access Memories  Serial access memories do not use an address Shift Registers Tapped Delay Lines Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO) 2355:035 Computer Architecture and Organization

Shift Register  Shift registers store and delay data  Simple design: cascade of registers Watch your hold times! 2455:035 Computer Architecture and Organization

Serial In Parallel Out  1-bit shift register reads in serial data After N steps, presents N-bit parallel output 2555:035 Computer Architecture and Organization

Parallel In Serial Out  Load all N bits in parallel when shift = 0 Then shift one bit out per cycle 2655:035 Computer Architecture and Organization

Queues  Queues allow data to be read and written at different rates.  Read and write each use their own clock, data  Queue indicates whether it is full or empty  Build with SRAM and read/write counters (pointers) 2755:035 Computer Architecture and Organization

FIFO, LIFO Queues First In First Out (FIFO)  Initialize read and write pointers to first element  Queue is EMPTY  On write, increment write pointer  If write almost catches read, Queue is FULL  On read, increment read pointer Last In First Out (LIFO)  Also called a stack  Use a single stack pointer for read and write 2855:035 Computer Architecture and Organization