1. 1 Pertemuan 17 Internal Memory: I Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

2. 2 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Menghubungkan konsep internal memory dalam mendesain sistem komputer ( C4 ) ( No TIK : 8 )

3. 3 Chapter 5. Internal Memory: I

4. 4 Up to 2 k addressable MDR MAR Figure 5.1. Connection of the memory to the processor. k-bit address bus n-bit data bus Control lines (, MFC, etc.) Processor Memory locations Word length =n bits WR/

5. 5 FF Figure 5.2. Organization of bit cells in a memory chip. circuit Sense / Write Address decoder FF CS cells Memory circuit Sense / Write circuit Data input/output lines: A 0 A 1 A 2 A 3 W 0 W 1 W 15 b 7 b 1 b 0 WR/ b 7 b 1 b 0 b 7 b 1 b 0

6. 6 Figure 5.3. Organization of a 1K  1 memory chip. CS Sense/Write circuitry array memory cell address 5-bit row input/output Data 5-bit decoder address 5-bit column address 10-bit output multiplexer 32-to-1 input demultiplexer 32  WR/ W 0 W 1 W 31 and

7. 7 YX Word line Bit lines Figure 5.4. A static RAM cell. b T 2 T 1 b

8. 8

9. 9 Figure 5.6. A single-transistor dynamic memory cell T C Word line Bit line

10. 10 Column CS Sense / Write circuits cell array latch address Row Column latch decoder Row decoder address 40965128  R/W A 209- A 80-  D 0 D 7 RAS CAS Figure 5.7. Internal organization of a 2M  8 dynamic memory chip.

11. 11 R/W RAS CAS CS Clock Cell array latch address Row decoder Row Figure 5.8. Synchronous DRAM. decoder Column Read/Write circuits & latches counter address Column Row/Column address Data input register Data output register Data Refresh counter Mode register and timing control

12. 12 R/W RAS CAS Clock Figure 5.9. Burst read of length 4 in an SDRAM. RowCol D0D1D2D3 Address Data

13. 13 Pertemuan 18 Internal Memory: II Matakuliah: T0324 / Arsitektur dan Organisasi Komputer Tahun: 2005 Versi: 1

14. 14 Learning Outcomes Pada akhir pertemuan ini, diharapkan mahasiswa akan mampu : Menghubungkan konsep internal memory dalam mendesain sistem komputer ( C4 ) ( No TIK : 8 )

15. 15 Chapter 5. Internal Memory: II

16. 16 Figure 5.10. Organization of a 2M  32 memory module using 512K  8 static memory chips. 19-bit internal chip address Chip select memory chip decoder 2-bit addresses 21-bit 19-bit address 512K8  A 0 A 1 A 19 memory chip A 20 D 31-24 D 7-0 D 23-16 D 15-8 512K8  8-bit data input/output

17. 17 Processor RAS CAS R/W Clock Address Row/Column address Memory controller R/W Clock Request CS Data Memory Figure 5.11. Use of a memory controller.

18. 18 Not connected to store a 1 Connected to store a 0 Figure 5.12. A ROM cell. Word line P Bit line T

19. 19 Processor Primary cache Secondary cache Main Magnetic disk memory Increasing size Increasing speed Figure 5.13. Memory hierarchy. secondary memory Increasing cost per bit Registers L1 L2

20. 20 Figure 5.14. Use of a cache memory. Cache Main memory Processor

21. 21 tag Cache Main memory Block 0 Block 1 Block 127 Block 128 Block 129 Block 255 Block 256 Block 257 Block 4095 Block 0 Block 1 Block 127 74Main memory address TagBlockWord Figure 5.15. Direct-mapped cache. 5

22. 22 4 tag Cache Main memory Block 0 Block 1 Blocki Block 4095 Block 0 Block 1 Block 127 12 Main memory address Figure 5.16. Associative-mapped cache. TagWord

23. 23 tag Cache Main memory Block 0 Block 1 Block 63 Block 64 Block 65 Block 127 Block 128 Block 129 Block 4095 Block 0 Block 1 Block 126 tag Block 2 Block 3 tag Block 127 Main memory address664 TagSetWord Set 0 Set 1 Set 63 Figure 5.17. Set-associative-mapped cache with two blocks per set.

24. 24 Figure 5.18. An array stored in the main memory. (7A00) (7A01) (7A02) (7A03) (7A04) (7A24) (7A25) (7A26) (7A27)