CSIE.NCTU, DL-6-1 Basic Design Approach of FSM Six Step Process 1. Understand the statement of the Specification 2. Obtain an abstract specification of the FSM 3. Perform a state minimization 4. Perform state assignment 5. Develop Verilog description of the FSM 6. Use logic synthesis tools to generate gate-level circuits 3, 4, can be done by logic synthesis tools

CSIE.NCTU, DL-6-2 Example: Vending Machine FSM General Machine Concept: deliver a can of coke-cola after 15 dollars deposited single coin slot for $5, $10 no change Block Diagram Step 1. Understand the problem: Vending Machine FSM 5 10 Reset Clk Open Coin Sensor Coke-cola Release Mechanism Draw a picture!

CSIE.NCTU, DL-6-3 Vending Machine Example Tabulate typical input sequences: three $5 $5, $10 $10, $5 two $10 two $5, %10 Draw state diagram: Inputs: F, T, reset Output: open Step 2. Map into more suitable abstract representation Reset F F F T T F T [open] S0 S1S2 S3 S4 S5 S6 S8 [open] S7 T

CSIE.NCTU, DL-6-4 Step 3: State Minimization Reset F F F, T [open] $15 $0 $5 $ 10 T F reuse states whenever possible Symbolic State Table Present State $0 $5 $10 $15 T X F X Inputs Next State $0 $5 $10 X $5 $10 15 X $10 15¢ X $0 Output Open X X X 1 Vending Machine Example

CSIE.NCTU, DL-6-5 Verilog Development Mealy machine or Moore machine? –If the outputs are functions of the internal state? Separate combinational circuits and FF’s –combinational circuits Boolean functions of next state Boolean functions of the outputs –FF’s current state <= next state