1. 50.002

2. Summary – Week 2 define what is combinational logic
state the static disciplines of combinational logic
write the truth table given a functional specification of a combinational device
write the sum-of-products of a boolean expression given a truth table or combinational logic, and vice versa
draw the combinational logic using NAND and NOR gates given the sum-of- products or truth table
simplify boolean expression using boolean algebra and Karnaugh map
explain the working of multiplexer
use multiplexer as universal gate implementation
implement boolean expression in read-only memory (ROM)

3. Outline Storage Elements Analysis of sequential circuits
Latch
Flip-Flop
Analysis of sequential circuits
State equations
State table
State diagram
Finite state machine
Mealy vs Moore
State reduction
State assignment
Design of sequential circuits

4. Sequential Logic Examples: Synchronous sequential Safety lock
Outputs depend on the sequence of inputs and “state”.
Combinational logic depend only on the present inputs.
Examples:
Safety lock
Traffic light
…..
Synchronous sequential
Asynchronous sequential
Synchronization through clock / clk

5. Simple Circuits with Feedback
“0”
“1”
Stored Value
Stored Value
Remember
Load
New Data

6. Settable Storage Element
It’s easy to build a settable storage element (called a latch) using a MUX:
Here’s a feedback path, so it’s no longer a combinational circuit. G 1 D -- Q’ Q
“state” signal
appears as both
input and output
Q follows D
Q stable D G Q A Q’ Y B 1 S

7. Actual D Latch Looks Like This (FYI)

8. Latch vs Flip-Flop
Latches: Storage elements that operate with signal levels (rather than signal transitions).
Level sensitive devices
Flip-flops: Storage elements that are controlled by a clock transition.
Edge sensitive devices

9. Flip-Flops

10. Master-Slave D Flip-Flop1
Y transfer to Q 1
Data transfer to Y
Try!!!!
A change in the output of the flip-flop can be triggered only by and during the transition of the clock from 1 to 0.

11. Graphical symbol D latch edge-triggered D flip-flop
Dynamic indicator = responds to edge transition
Functional Table
Characteristic Equation

12. Timing
Setup time: D input must maintained prior to the occurrence of the clock transition.
Hold time: D input must not change after the application of the positive transition of the clock.
Propagation delay: interval between the trigger edge and the stabilization of the output to a new state.

13. Outline Storage Elements Analysis of sequential circuits
Latch
Flip-Flop
Analysis of sequential circuits
State equations
State table
State diagram
Finite state machine
Mealy vs Moore
State reduction
State assignment
Design of sequential circuits

14. What is the function of this circuit?
T flip-flop is just another kind of flip-flop that is not covered.

15. Analysis of sequential circuits
Output = function (inputs and present state)
A sequential circuit can be represented by:
State Equation / Transition Equation
State table / Transition Table
State diagram

16. State Equations Any idea what is this circuit about?
A(t+1) = A(t)x + B(t)x
A(t+1) = Ax + Bx
Any idea what is this circuit about?
B(t+1) = A’(t)x
B(t+1) = A’x
Output
y = (A(t) + B(t))x’
y = (A + B)x’

17. State Table m flip-flops n inputs = 2m+n rows
A(t+1) = Ax + Bx
B(t+1) = A’x
y = (A + B)x’
m flip-flops
n inputs
= 2m+n rows
Any idea what is this circuit about?

18. State Diagram Any idea what is this circuit about?
Input / output
Any idea what is this circuit about?
State diagram gives a pictorial view of state transition,
more suitable for human interpretation.
The first “0” after a string of 1’s gives an output of 1, and transfer back to the initial state. Detect a “0” in the bit stream of data.

19. Analysis of Sequential Circuits
Circuit diagram  Equations  State table  State diagram
Input Equation
DA = Ax + Bx
DB = A’x
A(t+1) = Ax + Bx
B(t+1) = A’x

20. Example 1 – D Flip-Flop Write down the equation.
Write down the state table
Draw state diagram
Understand what is this circuit about

21. Finite State Machine
Mealy vs Moore
State reduction
State assignment

22. Two Models of Finite State Machine (FSM)
Output is a function of both present state and input
Output is a function of only the present state

23. Examples
Mealy
Output based on input and current state

24. Examples
Moore
Output depends only on current state

25. Mealy vs Moore
Mealy: outputs may change it the inputs change during the clock cycle.
Moore: Outputs are synchronized with the clock.

26. Analysis vs Design Analysis – Circuit diagram  state table / diagram
Design – Specifications  state diagram  circuit / HDL
Two sequential circuits may exhibit the same input-output behavior, but have a different number of internal states in their state diagram.
Simplify a design by reducing the number of gates and flip- flops use.

27. State Reduction Reduction in the number of flip-flops.
Reducing the number of states in a state table, while keeping the external input-output requirements unchanged.

28. Example
Two states are said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state.

30. State Reduction After State Reduction,
may or may not reduce the number of flip-flops.

31. State Assignment
Assign a unique coded binary values to the states.

32. Steps of Sequential Logic Design
Understand the problem
Obtain an abstract representation of the FSM
e.g. state diagram
Perform state minimization
Perform state assignment
Obtain state table
Implement the finite state machine
Hardwire: Choose the type of flip-flop
HDL

33. Example 2 – D Flip-Flop
Design a Moore circuit that detects a sequence of three or more consecutive 1’s.
Output: 1 after three or more consecutive 1’s.
0 otherwise
How many states we have?
How many bits required to represent them?
How many flip-flop needed?

34. Example 3: Three-Bit Up Counter
A 3-bit counter that counting up.

35. Example 4 - A Simple Vending Machine
Design a vending machine.
The vending machine delivers an item after it has received 15 cents in coins.
The machine has a single coin slot that accepts nickels (5 cents) and dimes (10 cents), one coin a time. Returns any coins it does not recognize.
Just need to design the state diagram.

36. Example 5 - Moore vs Mealy
Design two FSM that output “1” whenever its input string has at least two 1s in sequence.
One is Moore, another Mealy.
Design only the state diagram.

37. Two Models of Finite State Machine (FSM)
Output is a function of both present state and input
Output is a function of only the present state

38. Final Example - Lets build an Ant
SENSORS: antennae L and R, each 1 if in contact with something.
ACTUATORS: Forward Step F, ten-degree turns TL and TR (left, right).
8 legs?
GOAL: Make our ant smart enough to get out of a maze like:
STRATEGY: "Right antenna to the wall"

39. Action: Go forward until we hit something.
Lost in space ?
Action: Go forward until we hit something.
LOST F
L+R
_ _
L R
“lost” is the
initial state

40. Action: Turn left (CCW) until we don’t touch anymore
Bonk!
Action: Turn left (CCW) until we don’t touch anymore
LOST F
L+R
_ _
L R
RCCW TL
_ _

41. Action: Step and turn right a little, look for wall
A little to the right…
Action: Step and turn right a little, look for wall
L+R
LOST
L+R
RCCW F TL
_ _
L R R
_ _
L R
Wall1 _ R
TR,F

42. Then a little to the left
Action: Step and turn left a little, till not touching (again)
L+R _
L R
Wall2
LOST
L+R
RCCW F L
TL,F TL
_ _
L R R
_ _
L R
_ _
L R
Wall1 _ R
TR,F

43. Action: Step and turn right until we hit perpendicular wall
Dealing with corners
Action: Step and turn right until we hit perpendicular wall
L+R _
L R
Hey, this might
even work!
Wall2
LOST
L+R
RCCW F L
TL,F TL
_ _
L R R
_ _
L R
_ _
L R R _ R
Wall1
Corner _ R
TR,F
TR,F

44. Equivalent State Reduction
Observation: Si ≅ Sj if
1. States have identical outputs; AND
2. Every input ⇒equivalent states.
Reduction Strategy:
Find pairs of equivalent states, MERGE them.
L+R _
L R
Wall2
LOST
L+R
RCCW F L
TL,F TL
_ _
L R R
_ _
L R
_ _
L R R _ R
Wall1
Corner _ R
TR,F
TR,F

45. An Evolutionary Step
Merge equivalent states Wall1 and Corner into a single new, combined state.
L+R _
L R
Wall2
LOST
L+R
RCCW F L
TL,F TL
_ _
L R R
_ _
L R
_ _
L R
Wall1
TR,F _ R
Behaves exactly as previous (5-state) FSM, but requires half the ROM in its implementation!

46. Building the Transition Table
S L R | S’ TR TL F |
| | | |
| | |
LOST F
_ _
L R
L+R | | TL
L+R
RCCW

47. Implementation Details
S1’ S1S0 LR
S0’ S1S0 LR
S L R | S’ TR TL F |
| | | | |
10 – 0 | – 1 | | | |
LOST
RCCW
WALL1
WALL2
Complete Transition table

48. Ant Schematic

49. Good News #1
ANY digital circuit!!!!

50. Good News #2 Designer focus Synthesis tool Understand the problem
Obtain an abstract representation of the FSM
e.g. state diagram
Perform state minimization
Perform state assignment
Obtain state table
Implement the finite state machine
Hardwire: Choose the type of flip-flop
HDL
Synthesis tool

51. Summary – Week 3
draw the model of sequential logic consisting of memory device and combinational logic
explain the working of a D-latch
explain the working of edge-triggered flip-flop
analyze the relationship between setup time, hold time, contamination delay, and propagation delays.
define finite state machine and draw a valid state transition diagram given a specification
implement finite state machine in a hardware

52. Announcements
“Students can self-prepare one page of A4 cheat sheet for the Quiz”
Stick to original time schedule after week 3.